Back end of the line orback end of line (BEOL) is a process insemiconductor device fabrication that consists of depositing metalinterconnect layers onto a wafer already patterned with devices. It is the second part of IC fabrication, afterfront end of line (FEOL). In BEOL, the individual devices (transistors, capacitors, resistors, etc.) are connected to each other according to how the metal wiring is deposited.

The individual devices are connected by alternately stacking oxide layers(for insulation purposes) and metal layers (for the interconnect tracks). Thevias between layers and theinterconnects on the individual layers are thus formed using a structuring process.^[1]

Common metals arecopper andaluminum. BEOL generally begins when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. For modern IC processes, more than 10 metal layers can be added in the BEOL.

Before 1998, practically all chips used aluminium for the metal interconnection layers, whereas copper is mostly used nowadays.^[2]

Steps of the BEOL are:^[1][3]

1. Silicidation of source and drain regions and thepolysilicon region.
2. Adding a dielectric (first, lower layer ispre-metal dielectric (PMD) – to isolate metal from silicon and polysilicon),CMP processing it
3. Make holes in PMD, make a contacts in them.
4. Add metal layer 1
5. Add a second dielectric, called theinter-metal dielectric (IMD)
6. Make vias through dielectric to connect lower metal with higher metal. Vias filled byMetal CVD process.

   Repeat steps 4–6 to get all metal layers.

7. Add final passivation layer to protect the microchip

After BEOL there is a "back-end process" (also called post-fab), which is done not in the cleanroom, often by a different company.It includeswafer test,wafer backgrinding,die separation, die tests,IC packaging and final test.

• Front end of line (FEOL)
• Integrated circuit
• Phosphosilicate glass

• "Chapter 11: Back End Technology".Silicon VLSI Technology: Fundamentals, Practice, and Modeling. Prentice Hall. 2000. pp. 681–786.ISBN 0-13-085037-3.
• "Chapter 7.2.2: CMOS Process Integration: Backend-of-the-line Integration".CMOS: Circuit Design, Layout, and Simulation. Wiley-IEEE. 2010. pp. 199–208 [177–79].ISBN 978-0-470-88132-3.
• "Chapter 2: Technology Know-How: From Silicon to Devices".Fundamentals of Layout Design for Electronic Circuits, by Lienig, Scheible, Springer,doi:10.1007/978-3-030-39284-0ISBN 978-3-030-39284-0, 2020. p. 82 (2.9.4 BEOL: Connecting Devices)

• Electronics manufacturing
• Semiconductor device fabrication

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