Theasynchronous array of simple processors (AsAP) architecture comprises a 2-D array of reduced complexity programmable processors with smallscratchpad memories interconnected by a reconfigurablemesh network. AsAP was developed by researchers in the VLSI Computation Laboratory (VCL) at theUniversity of California, Davis and achieves high performance and energy efficiency, while using a relatively small circuit area. It was made in 2006.[1]
AsAP processors are well suited for implementation in future fabrication technologies, and are clocked in aglobally asynchronous locally synchronous (GALS) fashion. Individual oscillators fully halt (leakage only) in 9 cycles when there is no work to do, and restart at full speed in less than one cycle after work is available. The chip requires nocrystal oscillators,phase-locked loops,delay-locked loops, globalclock signal, or any global frequency or phase-related signals whatsoever.
The multi-processor architecture makes use of task-level parallelism in many complexdigital signal processor (DSP) applications, and also computes many large tasks usingfine-grained parallelism.
AsAP uses several novel key features, of which four are:
A chip containing 36 (6x6) programmable processors was taped-out in May 2005 in 0.18 μm CMOS using a synthesized standard cell technology and is fully functional. Processors on the chip operate at clock rates from 520 MHz to 540 MHz at 1.8V and each processor dissipates 32 mW on average while executing applications at 475 MHz.
Most processors run at clock rates over 600 MHz at 2.0 V, which makes AsAP among the highest known clock rate fabricated processors (programmable or non-programmable) ever designed in a university; it is the second highest known in published research papers.
At 0.9 V, the average application power per processor is 2.4 mW at 116 MHz. Each processor occupies 0.66 mm².
A second generation65 nm CMOS design contains 167 processors with dedicatedfast Fourier transform (FFT),Viterbi decoder, and videomotion estimation processors; 16 KB shared memories; and long-distance inter-processor interconnect. The programmable processors can individually and dynamicallychange their supply voltage andclock frequency. The chip is fully functional. Processors operate up to 1.2 GHz at 1.3 V which is believed to be the highest clock rate fabricated processor designed in any university. At 1.2 V, they operate at 1.07 GHz and 47 mW when 100% active. At 0.675 V, they operate at 66 MHz and 608 μW when 100% active. This operating point enables 1 trillionMAC orarithmetic logic unit (ALU) ops/sec with a power dissipation of only 9.2 watts. Due to itsMIMD architecture and fine-grain clock oscillator stalling, this energy efficiency per operation is almost perfectly constant across widely varying workloads, which is not the case for many architectures.
The coding of many DSP and general tasks for AsAP has been completed. Mapped tasks include: filters,convolutional coders, interleavers, sorting, square root,CORDIC sin/cos/arcsin/arccos,matrix multiplication, pseudo random number generators,fast Fourier transforms (FFTs) of lengths 32–1024, a complete k=7Viterbi decoder, aJPEG encoder, a complete fully compliant baseband processor for anIEEE 802.11a/g wireless LAN transmitter and receiver, and a completeCAVLC compression block for anH.264 encoder. Blocks plug directly together with no required modifications. Power, throughput, and area results are typically many times better than existing programmable DSP processors.
The architecture enables a clean separation between programming and inter-processor timing handled entirely by hardware. A recently finishedC compiler and automatic mapping tool further simplify programming.
