 | |
| Designer | |
|---|---|
| Bits | 32-bit,64-bit |
| Introduced | 1985; 40 years ago (1985) |
| Design | RISC |
| Type | Load–store |
| Branching | Condition code, compare and branch |
| Open | Proprietary |
 | |
| Introduced | 2011; 14 years ago (2011) |
|---|---|
| Version | ARMv8-R, ARMv8-A, ARMv8.1-A, ARMv8.2-A, ARMv8.3-A, ARMv8.4-A, ARMv8.5-A, ARMv8.6-A, ARMv8.7-A, ARMv8.8-A, ARMv8.9-A, ARMv9.0-A, ARMv9.1-A, ARMv9.2-A, ARMv9.3-A, ARMv9.4-A, ARMv9.5-A, ARMv9.6-A |
| Encoding | AArch64/A64 andAArch32/A32 use 32-bit instructions, AArch32/T32 (Thumb-2) uses mixed 16- and 32-bit instructions[1] |
| Endianness | Bi (little as default) |
| Extensions | SVE, SVE2, SME, AES, SM3, SM4, SHA, CRC32, RNDR, TME; All mandatory:Thumb-2,Neon, VFPv4-D16, VFPv4; obsolete:Jazelle |
| Registers | |
| General-purpose | 31 × 64-bit integer registers[1] |
| Floating point | 32 ×128-bit registers[1] for scalar 32- and 64-bitFP orSIMD FP or integer; or cryptography |
| Version | ARMv9-R, ARMv9-M, ARMv8-R, ARMv8-M, ARMv7-A, ARMv7-R, ARMv7E-M, ARMv7-M, ARMv6-M |
|---|---|
| Encoding | 32-bit, except Thumb-2 extensions use mixed 16- and 32-bit instructions. |
| Endianness | Bi (little as default) |
| Extensions | Thumb-2,Neon,Jazelle, AES, SM3, SM4, SHA, CRC32, RNDR, DSP, Saturated, FPv4-SP, FPv5, Helium |
| Registers | |
| General-purpose | 15 × 32-bit integer registers, including R14 (link register), but not R15 (PC) |
| Floating point | Up to 32 × 64-bit registers,[2] SIMD/floating-point (optional) |
| Version | ARMv6, ARMv5, ARMv4T, ARMv3, ARMv2 |
|---|---|
| Encoding | 32-bit, except Thumb extension uses mixed 16- and 32-bit instructions. |
| Endianness | Bi (little as default) in ARMv3 and above |
| Extensions | Thumb,Jazelle |
| Registers | |
| General-purpose | 15 × 32-bit integer registers, including R14 (link register), but not R15 (PC, 26-bit addressing in older) |
| Floating point | None |
ARM (stylised in lowercase asarm, formerly an acronym forAdvanced RISC Machines and originallyAcorn RISC Machine) is a family ofRISCinstruction set architectures (ISAs) forcomputer processors.Arm Holdings develops the ISAs and licenses them to other companies, who build the physical devices that use the instruction set. It also designs and licensescores that implement these ISAs.
Due to their low costs, low power consumption, and low heat generation, ARM processors are useful for light, portable, battery-powered devices, includingsmartphones,laptops, andtablet computers, as well asembedded systems.[3][4][5] However, ARM processors are also used fordesktops andservers, includingFugaku, the world's fastestsupercomputer from 2020[6] to 2022. With over 230 billion ARM chips produced,[7][8] since at least 2003, and with its dominance increasing every year[update], ARM is the most widely used family of instruction set architectures.[9][4][10][11][12]
There have been several generations of the ARM design. The original ARM1 used a32-bit internal structure but had a 26-bitaddress space that limited it to 64 MB ofmain memory. This limitation was removed in the ARMv3 series, which has a 32-bit address space, and several additional generations up to ARMv7 remained 32-bit. Released in 2011, the ARMv8-A architecture added support for a64-bit address space and 64-bit arithmetic with its new 32-bit fixed-length instruction set.[13] Arm Holdings has also released a series of additional instruction sets for different rules; the "Thumb" extension adds both 32- and 16-bit instructions for improvedcode density, whileJazelle added instructions for directly handlingJava bytecode. More recent changes include the addition ofsimultaneous multithreading (SMT) for improved performance orfault tolerance.[14]
Acorn Computers' first widely successful design was theBBC Micro, introduced in December 1981. This was a relatively conventional machine based on theMOS Technology 6502 CPU but ran at roughly double the performance of competing designs like theApple II due to its use of fasterdynamic random-access memory (DRAM). Typical DRAM of the era ran at about 2 MHz; Acorn arranged a deal withHitachi for a supply of faster 4 MHz parts.[15]
Machines of the era generally shared memory between the processor and theframebuffer, which allowed the processor to quickly update the contents of the screen without having to perform separateinput/output (I/O). As the timing of the video display is exacting, the video hardware had to have priority access to that memory. Due to a quirk of the 6502's design, the CPU left the memory untouched for half of the time. Thus by running the CPU at 1 MHz, the video system could read data during those down times, taking up the total 2 MHz bandwidth of the RAM. In the BBC Micro, the use of 4 MHz RAM allowed the same technique to be used, but running at twice the speed. This allowed it to outperform any similar machine on the market.[16]
1981 was also the year that theIBM Personal Computer was introduced. Using the recently introducedIntel 8088, a16-bit CPU compared to the 6502's8-bit design, it offered higher overall performance. Its introduction changed the desktop computer market radically: what had been largely a hobby and gaming market emerging over the prior five years began to change to a must-have business tool where the earlier 8-bit designs simply could not compete. Even newer32-bit designs were also coming to market, such as theMotorola 68000[17] andNational Semiconductor NS32016.[18]
Acorn began considering how to compete in this market and produced a new paper design named theAcorn Business Computer. They set themselves the goal of producing a machine with ten times the performance of the BBC Micro, but at the same price.[19] This would outperform and underprice the PC. At the same time, the recent introduction of theApple Lisa brought thegraphical user interface (GUI) concept to a wider audience and suggested the future belonged to machines with a GUI.[20] The Lisa, however, cost $9,995, as it was packed with support chips, large amounts of memory, and ahard disk drive, all very expensive then.[21]
The engineers then began studying all of the CPU designs available. Their conclusion about the existing 16-bit designs was that they were a lot more expensive and were still "a bit crap",[22] offering only slightly higher performance than their BBC Micro design. They also almost always demanded a large number of support chips to operate even at that level, which drove up the cost of the computer as a whole. These systems would simply not hit the design goal.[22] They also considered the new 32-bit designs, but these cost even more and had the same issues with support chips.[23] According toSophie Wilson, all the processors tested at that time performed about the same, with about a 4 Mbit/s bandwidth.[24][a]
Two key events led Acorn down the path to ARM. One was the publication of a series of reports from theUniversity of California, Berkeley, which suggested that a simple chip design could nevertheless have extremely high performance, much higher than the latest 32-bit designs on the market.[25] The second was a visit bySteve Furber and Sophie Wilson to theWestern Design Center, a company run byBill Mensch and his sister, which had become the logical successor to the MOS team and was offering new versions like theWDC 65C02. The Acorn team saw high school students producing chip layouts on Apple II machines, which suggested that anyone could do it.[26][27] In contrast, a visit to another design firm working on modern 32-bit CPU revealed a team with over a dozen members who were already on revision H of their design and yet it still contained bugs.[b] This cemented their late 1983 decision to begin their own CPU design, the Acorn RISC Machine.[28]
The originalBerkeley RISC designs were in some sense teaching systems, not designed specifically for outright performance. To the RISC's basic register-heavy and load/store concepts, ARM added a number of the well-received design notes of the 6502. Primary among them was the ability to quickly serveinterrupts, which allowed the machines to offer reasonableinput/output performance with no added external hardware. To offer interrupts with similar performance as the 6502, the ARM design limited its physicaladdress space to 64 MB of total addressable space, requiring 26 bits of address. As instructions were 4 bytes (32 bits) long, and required to be aligned on 4-byte boundaries, the lower 2 bits of an instruction address were always zero. This meant theprogram counter (PC) only needed to be 24 bits, allowing it to be stored along with the eight bitprocessor flags in a single 32-bit register. That meant that upon receiving an interrupt, the entire machine state could be saved in a single operation, whereas had the PC been a full 32-bit value, it would require separate operations to store the PC and the status flags. This decision halved the interrupt overhead.[29]
Another change, and among the most important in terms of practical real-world performance, was the modification of theinstruction set to take advantage ofpage mode DRAM. Recently introduced, page mode allowed subsequent accesses of memory to run twice as fast if they were roughly in the same location, or "page", in the DRAM chip. Berkeley's design did not consider page mode and treated all memory equally. The ARM design added special vector-like memory access instructions, the "S-cycles", that could be used to fill or save multiple registers in a single page using page mode. This doubled memory performance when they could be used, and was especially important for graphics performance.[30]
The Berkeley RISC designs usedregister windows to reduce the number of register saves and restores performed inprocedure calls; the ARM design did not adopt this.
Wilson developed the instruction set, writing a simulation of the processor inBBC BASIC that ran on a BBC Micro with asecond 6502 processor.[31][32] This convinced Acorn engineers they were on the right track. Wilson approached Acorn's CEO,Hermann Hauser, and requested more resources. Hauser gave his approval and assembled a small team to design the actual processor based on Wilson's ISA.[33] The official Acorn RISC Machine project started in October 1983.
Acorn choseVLSI Technology as the "silicon partner", as they were a source of ROMs and custom chips for Acorn. Acorn provided the design and VLSI provided the layout and production. The first samples of ARM silicon worked properly when first received and tested on 26 April 1985.[3] Known as ARM1, these versions ran at 6 MHz.[34]
The first ARM application was as a second processor for the BBC Micro, where it helped in developing simulation software to finish development of the support chips (VIDC, IOC, MEMC), and sped up theCAD software used in ARM2 development. Wilson subsequently rewroteBBC BASIC in ARMassembly language. The in-depth knowledge gained from designing the instruction set enabled the code to be very dense, making ARM BBC BASIC an extremely good test for any ARM emulator.
The result of the simulations on the ARM1 boards led to the late 1986 introduction of the ARM2 design running at 8 MHz, and the early 1987 speed-bumped version at 10 to 12 MHz.[c] A significant change in the underlying architecture was the addition of aBooth multiplier, whereas formerly multiplication had to be carried out in software.[36] Further, a new Fast Interrupt reQuest mode, FIQ for short, allowed registers 8 through 14 to be replaced as part of the interrupt itself. This meant FIQ requests did not have to save out their registers, further speeding interrupts.[37]
The first use of the ARM2 was theAcorn Archimedes personal computer models A305, A310, and A440 launched in 1987.
According to theDhrystone benchmark, the ARM2 was roughly seven times the performance of a typical 7 MHz 68000-based system like theAmiga orMacintosh SE. It was twice as fast as anIntel 80386 running at 16 MHz, and about the same speed as a multi-processorVAX-11/784superminicomputer. The only systems that beat it were theSun SPARC andMIPS R2000 RISC-basedworkstations.[38] Further, as the CPU was designed for high-speed I/O, it dispensed with many of the support chips seen in these machines; notably, it lacked any dedicateddirect memory access (DMA) controller which was often found on workstations. The graphics system was also simplified based on the same set of underlying assumptions about memory and timing. The result was a dramatically simplified design, offering performance on par with expensive workstations but at a price point similar to contemporary desktops.[38]
The ARM2 featured a32-bitdata bus,26-bit address space and 27 32-bitregisters, of which 16 are accessible at any one time (including thePC).[39] The ARM2 had atransistor count of just 30,000,[40] compared to Motorola's six-year-older 68000 model with around 68,000. Much of this simplicity came from the lack ofmicrocode, which represents about one-quarter to one-third of the 68000's transistors, and the lack of (like most CPUs of the day) acache. This simplicity enabled the ARM2 to have a low power consumption and simpler thermal packaging by having fewer powered transistors. Nevertheless, ARM2 offered better performance than the contemporary 1987IBM PS/2 Model 50, which initially utilised anIntel 80286, offering 1.8 MIPS @ 10 MHz, and later in 1987, the 2 MIPS of the PS/2 70, with itsIntel 386 DX @ 16 MHz.[41][42]
A successor, ARM3, was produced with a 4 KB cache, which further improved performance.[43] The address bus was extended to 32 bits in the ARM6, but program code still had to lie within the first 64 MB of memory in 26-bit compatibility mode, due to the reserved bits for the status flags.[44]
In the late 1980s,Apple Computer andVLSI Technology started working with Acorn on newer versions of the ARM core. In 1990, Acorn spun off the design team into a new company named Advanced RISC Machines Ltd.,[45][46][47] which became ARM Ltd. when its parent company,Arm Holdings plc, floated on theLondon Stock Exchange andNasdaq in 1998.[48] The new Apple–ARM work would eventually evolve into the ARM6, first released in early 1992. Apple used the ARM6-based ARM610 as the basis for theirApple Newton PDA.
In 1994, Acorn used the ARM610 as the maincentral processing unit (CPU) in theirRiscPC computers.DEC licensed the ARMv4 architecture and produced theStrongARM.[49] At 233 MHz, this CPU drew only one watt (newer versions draw far less). This work was later passed to Intel as part of a lawsuit settlement, and Intel took the opportunity to supplement theiri960 line with the StrongARM. Intel later developed its own high performance implementation namedXScale, which it has since sold toMarvell. Transistor count of the ARM core remained essentially the same throughout these changes; ARM2 had 30,000 transistors,[50] while ARM6 grew only to 35,000.[51]
In 2005, about 98% of all mobile phones sold used at least one ARM processor.[52] In 2010, producers of chips based on ARM architectures reported shipments of 6.1 billionARM-based processors, representing 95% ofsmartphones, 35% ofdigital televisions andset-top boxes, and 10% ofmobile computers. In 2011, the 32-bit ARM architecture was the most widely used architecture in mobile devices and the most popular 32-bit one in embedded systems.[53] In 2013, 10 billion were produced[54] and "ARM-based chips are found in nearly 60 percent of the world's mobile devices".[55]
Arm Holdings's primary business is sellingIP cores, which licensees use to createmicrocontrollers (MCUs),CPUs, andsystems-on-chips based on those cores. Theoriginal design manufacturer combines the ARM core with other parts to produce a complete device, typically one that can be built in existingsemiconductor fabrication plants (fabs) at low cost and still deliver substantial performance. The most successful implementation has been theARM7TDMI with hundreds of millions sold.Atmel has been a precursor design center in the ARM7TDMI-based embedded system.
The ARM architectures used in smartphones, PDAs and othermobile devices range from ARMv5 toARMv8-A.
In 2009, some manufacturers introduced netbooks based on ARM architecture CPUs, in direct competition with netbooks based onIntel Atom.[56]
Arm Holdings offers a variety of licensing terms, varying in cost and deliverables. Arm Holdings provides to all licensees an integratable hardware description of the ARM core as well as complete software development toolset (compiler,debugger,software development kit), and the right to sell manufacturedsilicon containing the ARM CPU.
SoC packages integrating ARM's core designs include Nvidia Tegra's first three generations, CSR plc's Quatro family, ST-Ericsson's Nova and NovaThor, Silicon Labs's Precision32 MCU, Texas Instruments'sOMAP products, Samsung's Hummingbird andExynos products, Apple'sA4,A5, andA5X, andNXP'si.MX.
Fabless licensees, who wish to integrate an ARM core into their own chip design, are usually only interested in acquiring a ready-to-manufacture verifiedsemiconductor intellectual property core. For these customers, Arm Holdings delivers agate netlist description of the chosen ARM core, along with an abstracted simulation model and test programs to aid design integration and verification. More ambitious customers, including integrated device manufacturers (IDM) and foundry operators, choose to acquire the processor IP insynthesizableRTL (Verilog) form. With the synthesizable RTL, the customer has the ability to perform architectural level optimisations and extensions. This allows the designer to achieve exotic design goals not otherwise possible with an unmodified netlist (high clock speed, very low power consumption, instruction set extensions, etc.). While Arm Holdings does not grant the licensee the right to resell the ARM architecture itself, licensees may freely sell manufactured products such as chip devices, evaluation boards and complete systems.Merchant foundries can be a special case; not only are they allowed to sell finished silicon containing ARM cores, they generally hold the right to re-manufacture ARM cores for other customers.
Arm Holdings prices its IP based on perceived value. Lower performing ARM cores typically have lower licence costs than higher performing cores. In implementation terms, a synthesisable core costs more than a hard macro (blackbox) core. Complicating price matters, a merchant foundry that holds an ARM licence, such as Samsung or Fujitsu, can offer fab customers reduced licensing costs. In exchange for acquiring the ARM core through the foundry's in-house design services, the customer can reduce or eliminate payment of ARM's upfront licence fee.
Compared to dedicated semiconductor foundries (such asTSMC andUMC) without in-house design services, Fujitsu/Samsung charge two- to three-times more per manufacturedwafer.[citation needed] For low to mid volume applications, a design service foundry offers lower overall pricing (through subsidisation of the licence fee). For high volume mass-produced parts, the long term cost reduction achievable through lower wafer pricing reduces the impact of ARM's NRE (non-recurring engineering) costs, making the dedicated foundry a better choice.
Companies that have developed chips with cores designed by Arm includeAmazon.com'sAnnapurna Labs subsidiary,[57]Analog Devices,Apple,AppliedMicro (now:MACOM Technology Solutions[58]),Atmel,Broadcom,Cavium,Cypress Semiconductor,Freescale Semiconductor (nowNXP Semiconductors),Huawei,Intel,[dubious –discuss]Maxim Integrated,Nvidia,NXP,Qualcomm,Renesas,Samsung Electronics,ST Microelectronics,Texas Instruments, andXilinx.
In February 2016, ARM announced the Built on ARM Cortex Technology licence, often shortened to Built on Cortex (BoC) licence. This licence allows companies to partner with ARM and make modifications to ARM Cortex designs. These design modifications will not be shared with other companies. These semi-custom core designs also have brand freedom, for exampleKryo 280.
Companies that are current licensees of Built on ARM Cortex Technology includeQualcomm.[59]
Companies can also obtain an ARMarchitectural licence for designing their own CPU cores using the ARM instruction sets. These cores must comply fully with the ARM architecture. Companies that have designed cores that implement an ARM architecture include Apple, AppliedMicro (now:Ampere Computing), Broadcom,Cavium (now: Marvell),Digital Equipment Corporation, Intel, Nvidia, Qualcomm, Samsung Electronics,Fujitsu, and NUVIA Inc. (acquired by Qualcomm in 2021).
On 16 July 2019, ARM announced ARM Flexible Access. ARM Flexible Access provides unlimited access to included ARMintellectual property (IP) for development. Per product licence fees are required once a customer reaches foundry tapeout or prototyping.[60][61]
75% of ARM's most recent IP over the last two years are included in ARM Flexible Access. As of October 2019:
| Architecture | Core bit-width | Cores | Profile | Refe- rences | |
|---|---|---|---|---|---|
| Arm Ltd. | Third-party | ||||
ARMv1 | ARM1 | Classic | |||
ARMv2 | 32 | ARM2, ARM250,ARM3 | Amber, STORM Open Soft Core[62] | Classic | |
ARMv3 | 32 | ARM6,ARM7 | Classic | ||
ARMv4 | 32 | ARM8 | StrongARM, FA526, ZAP Open Source Processor Core | Classic | |
ARMv4T | 32 | ARM7TDMI,ARM9TDMI,SecurCore SC100 | Classic | ||
ARMv5TE | 32 | ARM7EJ,ARM9E,ARM10E | XScale, FA626TE, Feroceon, PJ1/Mohawk | Classic | |
ARMv6 | 32 | ARM11 | Classic | ||
ARMv6-M | 32 | ARM Cortex-M0,ARM Cortex-M0+,ARM Cortex-M1,SecurCore SC000 | |||
ARMv7-M | 32 | ARM Cortex-M3,SecurCore SC300 | Apple M7 motion coprocessor | Microcontroller | |
ARMv7E-M | 32 | ARM Cortex-M4,ARM Cortex-M7 | Microcontroller | ||
ARMv8-M | 32 | ARM Cortex-M23,[64]ARM Cortex-M33[65] | Microcontroller | ||
ARMv8.1-M | 32 | ARM Cortex-M55,ARM Cortex-M85 | Microcontroller | ||
ARMv7-R | 32 | ARM Cortex-R4,ARM Cortex-R5,ARM Cortex-R7,ARM Cortex-R8 | |||
ARMv8-R | 32 | ARM Cortex-R52 | Real-time | ||
64 | ARM Cortex-R82 | Real-time | |||
ARMv7-A | 32 | ARM Cortex-A5,ARM Cortex-A7,ARM Cortex-A8,ARM Cortex-A9,ARM Cortex-A12,ARM Cortex-A15,ARM Cortex-A17 | QualcommScorpion/Krait, PJ4/Sheeva, Apple Swift (A6,A6X) | ||
ARMv8-A | 32 | ARM Cortex-A32[71] | Application | ||
64/32 | ARM Cortex-A35,[72]ARM Cortex-A53,ARM Cortex-A57,[73]ARM Cortex-A72,[74]ARM Cortex-A73[75] | X-Gene,Nvidia Denver 1/2,Cavium ThunderX,AMD K12, Apple Cyclone (A7)/Typhoon (A8,A8X)/Twister (A9,A9X)/Hurricane+Zephyr (A10,A10X),QualcommKryo, Samsung M1/M2 ("Mongoose") /M3 ("Meerkat") | Application | ||
| ARM Cortex-A34[81] | Application | ||||
ARMv8.1-A | 64/32 | TBA | Cavium ThunderX2 | Application | |
ARMv8.2-A | 64/32 | ARM Cortex-A55,[83]ARM Cortex-A75,[84]ARM Cortex-A76,[85]ARM Cortex-A77,ARM Cortex-A78,ARM Cortex-X1,ARM Neoverse N1 | Nvidia Carmel, Samsung M4 ("Cheetah"),Fujitsu A64FX (ARMv8 SVE 512-bit) | Application | |
64 | ARM Cortex-A65,ARM Neoverse E1 withsimultaneous multithreading (SMT),ARM Cortex-A65AE[89] (also having e.g. ARMv8.4 Dot Product; made for safety critical tasks such asadvanced driver-assistance systems (ADAS)) | Apple Monsoon+Mistral (A11) (September 2017) | Application | ||
ARMv8.3-A | 64/32 | TBA | Application | ||
64 | TBA | Apple Vortex+Tempest (A12,A12X,A12Z), Marvell ThunderX3 (v8.3+)[90] | Application | ||
ARMv8.4-A | 64/32 | TBA | Application | ||
64 | ARM Neoverse V1 | Apple Lightning+Thunder (A13), Apple Firestorm+Icestorm (A14,M1) | Application | ||
ARMv8.5-A | 64/32 | TBA | Application | ||
64 | TBA | Application | |||
ARMv8.6-A | 64 | TBA | Apple Avalanche+Blizzard (A15,M2), Apple Everest+Sawtooth (A16),[91]A17 | Application | |
ARMv8.7-A | 64 | TBA | Application | ||
ARMv8.8-A | 64 | TBA | Application | ||
ARMv8.9-A | 64 | TBA | Application | ||
ARMv9.0-A | 64 | ARM Cortex-A510,ARM Cortex-A710,ARM Cortex-A715,ARM Cortex-X2,ARM Cortex-X3,ARM Neoverse E2,ARM Neoverse N2,ARM Neoverse V2 | Application | ||
ARMv9.1-A | 64 | TBA | Application | ||
ARMv9.2-A | 64 | ARM Cortex-A520,ARM Cortex-A720,ARM Cortex-X4,ARM Neoverse V3,[95]ARM Cortex-X925[96] | Apple M4,[97]A18 | Application | |
ARMv9.3-A | 64 | TBA | Application | ||
ARMv9.4-A | 64 | TBA | Application | ||
ARMv9.5-A | 64 | TBA | Application | ||
ARMv9.6-A | 64 | TBA | Application | ||
Arm provides a list of vendors who implement ARM cores in their design (application specific standard products (ASSP), microprocessor and microcontrollers).[102]
ARM cores are used in a number of products, particularlyPDAs andsmartphones. Somecomputing examples areMicrosoft'sfirst generation Surface,Surface 2 andPocket PC devices (following2002),Apple'siPads, andAsus'sEee Pad Transformertablet computers, and severalChromebook laptops. Others include Apple'siPhonesmartphones andiPodportable media players,Canon PowerShotdigital cameras,Nintendo Switch hybrid, theWii security processor and3DShandheld game consoles, andTomTom turn-by-turnnavigation systems.
In 2005, Arm took part in the development ofManchester University's computerSpiNNaker, which used ARM cores to simulate thehuman brain.[103]
ARM chips are also used inRaspberry Pi,BeagleBoard,BeagleBone,PandaBoard, and othersingle-board computers, because they are very small, inexpensive, and consume very little power.
The 32-bit ARM architecture (ARM32), such asARMv7-A (implementing AArch32; seesection on Armv8-A for more on it), was the most widely used architecture in mobile devices as of 2011[update].[53]
Since 1995, various versions of theARM Architecture Reference Manual (see§ External links) have been the primary source of documentation on the ARM processor architecture and instruction set, distinguishing interfaces that all ARM processors are required to support (such as instruction semantics) from implementation details that may vary. The architecture has evolved over time, and version seven of the architecture, ARMv7, defines three architecture "profiles":
Although the architecture profiles were first defined for ARMv7, ARM subsequently defined the ARMv6-M architecture (used by the CortexM0/M0+/M1) as a subset of the ARMv7-M profile with fewer instructions.
Except in the M-profile, the 32-bit ARM architecture specifies several CPU modes, depending on the implemented architecture features. At any moment in time, the CPU can be in only one mode, but it can switch modes due to external events (interrupts) or programmatically.[104]
The original (and subsequent) ARM implementation was hardwired withoutmicrocode, like the much simpler8-bit6502 processor used in prior Acorn microcomputers.
The 32-bit ARM architecture (and the 64-bit architecture for the most part) includes the following RISC features:
To compensate for the simpler design, compared with processors like the Intel 80286 andMotorola 68020, some additional design features were used:
ARM includes integer arithmetic operations for add, subtract, and multiply; some versions of the architecture also support divide operations.
ARM supports 32-bit × 32-bit multiplies with either a 32-bit result or 64-bit result, though Cortex-M0 / M0+ / M1 cores do not support 64-bit results.[109] Some ARM cores also support 16-bit × 16-bit and 32-bit × 16-bit multiplies.
The divide instructions are only included in the following ARM architectures:
| usr | sys | svc | abt | und | irq | fiq |
|---|---|---|---|---|---|---|
| R0 | ||||||
| R1 | ||||||
| R2 | ||||||
| R3 | ||||||
| R4 | ||||||
| R5 | ||||||
| R6 | ||||||
| R7 | ||||||
| R8 | R8_fiq | |||||
| R9 | R9_fiq | |||||
| R10 | R10_fiq | |||||
| R11 | R11_fiq | |||||
| R12 | R12_fiq | |||||
| R13 | R13_svc | R13_abt | R13_und | R13_irq | R13_fiq | |
| R14 | R14_svc | R14_abt | R14_und | R14_irq | R14_fiq | |
| R15 | ||||||
| CPSR | ||||||
| SPSR_svc | SPSR_abt | SPSR_und | SPSR_irq | SPSR_fiq | ||
Registers R0 through R7 are the same across all CPU modes; they are never banked.
Registers R8 through R12 are the same across all CPU modes except FIQ mode. FIQ mode has its own distinct R8 through R12 registers.
R13 and R14 are banked across all privileged CPU modes except system mode. That is, each mode that can be entered because of an exception has its own R13 and R14. These registers generally contain the stack pointer and the return address from function calls, respectively.
Aliases:
The Current Program Status Register (CPSR) has the following 32 bits.[112]
Almost every ARM instruction has a conditional execution feature calledpredication, which is implemented with a 4-bit condition code selector (the predicate). To allow for unconditional execution, one of the four-bit codes causes the instruction to be always executed. Most other CPU architectures only have condition codes on branch instructions.[113]
Though the predicate takes up four of the 32 bits in an instruction code, and thus cuts down significantly on the encoding bits available for displacements in memory access instructions, it avoids branch instructions when generating code for smallif statements. Apart from eliminating the branch instructions themselves, this preserves the fetch/decode/execute pipeline at the cost of only one cycle per skipped instruction.
An algorithm that provides a good example of conditional execution is the subtraction-basedEuclidean algorithm for computing thegreatest common divisor. In theC programming language, the algorithm can be written as:
intgcd(inta,intb){while(a!=b)// We enter the loop when a < b or a > b, but not when a == bif(a>b)// When a > b we do thisa-=b;else// When a < b we do that (no "if (a < b)" needed since a != b is checked in while condition)b-=a;returna;}
The same algorithm can be rewritten in a way closer to target ARMinstructions as:
loop:// Compare a and bGT=a>b;LT=a<b;NE=a!=b;// Perform operations based on flag resultsif(GT)a-=b;// Subtract *only* if greater-thanif(LT)b-=a;// Subtract *only* if less-thanif(NE)gotoloop;// Loop *only* if compared values were not equalreturna;
and coded inassembly language as:
; assign a to register r0, b to r1loop:CMPr0,r1; set condition "NE" if (a ≠ b),; "GT" if (a > b),; or "LT" if (a < b)SUBGTr0,r0,r1; if "GT" (Greater Than), then a = a − bSUBLTr1,r1,r0; if "LT" (Less Than), then b = b − aBNEloop; if "NE" (Not Equal), then loopBlr; return
which avoids the branches around thethen andelse clauses. Ifr0 andr1 are equal then neither of theSUB instructions will be executed, eliminating the need for a conditional branch to implement thewhile check at the top of the loop, for example hadSUBLE (less than or equal) been used.
One of the ways that Thumb code provides a more dense encoding is to remove the four-bit selector from non-branch instructions.
Another feature of theinstruction set is the ability to fold shifts and rotates into thedata processing (arithmetic, logical, and register-register move) instructions, so that, for example, the statement inC language:
a+=(j<<2);
could be rendered as a one-word, one-cycle instruction:[114]
ADDRa,Ra,Rj,LSL#2
This results in the typical ARM program being denser than expected with fewer memory accesses; thus the pipeline is used more efficiently.
The ARM processor also has features rarely seen in other RISC architectures, such asPC-relative addressing (indeed, on the 32-bit[1] ARM thePC is one of its 16 registers) and pre- and post-increment addressing modes.
The ARM instruction set has increased over time. Some early ARM processors (before ARM7TDMI), for example, have no instruction to store a two-byte quantity.
The ARM7 and earlier implementations have a three-stagepipeline; the stages being fetch, decode, and execute. Higher-performance designs, such as the ARM9, have deeper pipelines: Cortex-A8 has thirteen stages. Additional implementation changes for higher performance include a fasteradder and more extensivebranch prediction logic. The difference between the ARM7DI and ARM7DMI cores, for example, was an improved multiplier; hence the added "M".
The ARM architecture (pre-Armv8) provides a non-intrusive way of extending the instruction set using "coprocessors" that can be addressed using MCR, MRC, MRRC, MCRR, and similar instructions. The coprocessor space is divided logically into 16 coprocessors with numbers from 0 to 15, coprocessor 15 (cp15) being reserved for some typical control functions like managing the caches andMMU operation on processors that have one.
In ARM-based machines, peripheral devices are usually attached to the processor by mapping their physical registers into ARM memory space, into the coprocessor space, or by connecting to another device (a bus) that in turn attaches to the processor. Coprocessor accesses have lower latency, so some peripherals—for example, an XScale interrupt controller—are accessible in both ways: through memory and through coprocessors.
In other cases, chip designers only integrate hardware using the coprocessor mechanism. For example, an image processing engine might be a small ARM7TDMI core combined with a coprocessor that has specialised operations to support a specific set of HDTV transcoding primitives.
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All modern ARM processors include hardware debugging facilities, allowing software debuggers to perform operations such as halting, stepping, and breakpointing of code starting from reset. These facilities are built usingJTAG support, though some newer cores optionally support ARM's own two-wire "SWD" protocol. In ARM7TDMI cores, the "D" represented JTAG debug support, and the "I" represented presence of an "EmbeddedICE" debug module. For ARM7 and ARM9 core generations, EmbeddedICE over JTAG was a de facto debug standard, though not architecturally guaranteed.
The ARMv7 architecture defines basic debug facilities at an architectural level. These include breakpoints, watchpoints and instruction execution in a "Debug Mode"; similar facilities were also available with EmbeddedICE. Both "halt mode" and "monitor" mode debugging are supported. The actual transport mechanism used to access the debug facilities is not architecturally specified, but implementations generally include JTAG support.
There is a separate ARM "CoreSight" debug architecture, which is not architecturally required by ARMv7 processors.
The Debug Access Port (DAP) is an implementation of an ARM Debug Interface.[115]There are two different supported implementations, the Serial WireJTAG Debug Port (SWJ-DP) and the Serial Wire Debug Port (SW-DP).[116]CMSIS-DAP is a standard interface that describes how various debugging software on a host PC can communicate over USB to firmware running on a hardware debugger, which in turn talks over SWD or JTAG to a CoreSight-enabled ARM Cortex CPU.[117][118][119]
To improve the ARM architecture fordigital signal processing and multimedia applications, DSP instructions were added to the instruction set.[120] These are signified by an "E" in the name of the ARMv5TE and ARMv5TEJ architectures. E-variants also imply T, D, M, and I.
The new instructions are common indigital signal processor (DSP) architectures. They include variations on signedmultiply–accumulate,saturated add and subtract, andcount leading zeros.
First introduced in 1999, this extension of the core instruction set contrasted with ARM's earlier DSP coprocessor known as Piccolo, which employed a distinct, incompatible instruction set whose execution involved a separate program counter.[121] Piccolo instructions employed a distinct register file of sixteen 32-bit registers, with some instructions combining registers for use as 48-bit accumulators and other instructions addressing 16-bit half-registers. Some instructions were able to operate on two such 16-bit values in parallel. Communication with the Piccolo register file involvedload to Piccolo andstore from Piccolo coprocessor instructions via two buffers of eight 32-bit entries. Described as reminiscent of other approaches, notably Hitachi's SH-DSP and Motorola's 68356, Piccolo did not employ dedicated local memory and relied on the bandwidth of the ARM core for DSP operand retrieval, impacting concurrent performance.[122] Piccolo's distinct instruction set also proved not to be a "good compiler target".[121]
Introduced in the ARMv6 architecture, this was a precursor to Advanced SIMD, also namedNeon.[123]
Jazelle DBX (Direct Bytecode eXecution) is a technique that allowsJava bytecode to be executed directly in the ARM architecture as a third execution state (and instruction set) alongside the existing ARM and Thumb-mode. Support for this state is signified by the "J" in the ARMv5TEJ architecture, and in ARM9EJ-S and ARM7EJ-S core names. Support for this state is required starting in ARMv6 (except for the ARMv7-M profile), though newer cores only include a trivial implementation that provides no hardware acceleration.
To improve compiled code density, processors since the ARM7TDMI (released in 1994[124]) have featured theThumbcompressed instruction set, which have their own state. (The "T" in "TDMI" indicates the Thumb feature.) When in this state, the processor executes the Thumb instruction set, a compact 16-bit encoding for a subset of the ARM instruction set.[125] Most of the Thumb instructions are directly mapped to normal ARM instructions. The space saving comes from making some of the instruction operands implicit and limiting the number of possibilities compared to the ARM instructions executed in the ARM instruction set state.
In Thumb, the 16-bit opcodes have less functionality. For example, only branches can be conditional, and many opcodes are restricted to accessing only half of all of the CPU's general-purpose registers. The shorter opcodes give improved code density overall, even though some operations require extra instructions. In situations where the memory port or bus width is constrained to less than 32 bits, the shorter Thumb opcodes allow increased performance compared with 32-bit ARM code, as less program code may need to be loaded into the processor over the constrained memory bandwidth.
Unlike processor architectures with variable length (16- or 32-bit) instructions, such as the Cray-1 andHitachiSuperH, the ARM and Thumb instruction sets exist independently of each other. Embedded hardware, such as theGame Boy Advance, typically have a small amount of RAM accessible with a full 32-bit datapath; the majority is accessed via a 16-bit or narrower secondary datapath. In this situation, it usually makes sense to compile Thumb code and hand-optimise a few of the most CPU-intensive sections using full 32-bit ARM instructions, placing these wider instructions into the 32-bit bus accessible memory.
The first processor with a Thumbinstruction decoder was the ARM7TDMI. All processors supporting 32-bit instruction sets, starting with ARM9, and including XScale, have included a Thumb instruction decoder. It includes instructions adopted from the HitachiSuperH (1992), which was licensed by ARM.[126] ARM's smallest processor families (Cortex M0 and M1) implement only the 16-bit Thumb instruction set for maximum performance in lowest cost applications. ARM processors that don't support 32-bit addressing also omit Thumb.
Thumb-2 technology was introduced in theARM1156 core, announced in 2003. Thumb-2 extends the limited 16-bit instruction set of Thumb with additional 32-bit instructions to give the instruction set more breadth, thus producing a variable-length instruction set. A stated aim for Thumb-2 was to achieve code density similar to Thumb with performance similar to the ARM instruction set on 32-bit memory.
Thumb-2 extends the Thumb instruction set with bit-field manipulation, table branches and conditional execution. At the same time, the ARM instruction set was extended to maintain equivalent functionality in both instruction sets. A new "Unified Assembly Language" (UAL) supports generation of either Thumb or ARM instructions from the same source code; versions of Thumb seen on ARMv7 processors are essentially as capable as ARM code (including the ability to write interrupt handlers). This requires a bit of care, and use of a new "IT" (if-then) instruction, which permits up to four successive instructions to execute based on a tested condition, or on its inverse. When compiling into ARM code, this is ignored, but when compiling into Thumb it generates an actual instruction. For example:
; if (r0 == r1)CMPr0,r1ITEEQ; ARM: no code ... Thumb: IT instruction; then r0 = r2;MOVEQr0,r2; ARM: conditional; Thumb: condition via ITE 'T' (then); else r0 = r3;MOVNEr0,r3; ARM: conditional; Thumb: condition via ITE 'E' (else); recall that the Thumb MOV instruction has no bits to encode "EQ" or "NE".
All ARMv7 chips support the Thumb instruction set. All chips in the Cortex-A series that support ARMv7, all Cortex-R series, and all ARM11 series support both "ARM instruction set state" and "Thumb instruction set state", while chips in theCortex-M series support only the Thumb instruction set.[127][128][129]
ThumbEE (erroneously calledThumb-2EE in some ARM documentation), which was marketed as Jazelle RCT[130] (Runtime Compilation Target), was announced in 2005 and deprecated in 2011. It first appeared in theCortex-A8 processor. ThumbEE is a fourth instruction set state, making small changes to the Thumb-2 extended instruction set. These changes make the instruction set particularly suited to code generated at runtime (e.g. byJIT compilation) in managedExecution Environments. ThumbEE is a target for languages such asJava,C#,Perl, andPython, and allowsJIT compilers to output smaller compiled code without reducing performance.[citation needed]
New features provided by ThumbEE include automatic null pointer checks on every load and store instruction, an instruction to perform an array bounds check, and special instructions that call a handler. In addition, because it utilises Thumb-2 technology, ThumbEE provides access to registers r8–r15 (where the Jazelle/DBX Java VM state is held).[131] Handlers are small sections of frequently called code, commonly used to implement high level languages, such as allocating memory for a new object. These changes come from repurposing a handful of opcodes, and knowing the core is in the new ThumbEE state.
On 23 November 2011, Arm deprecated any use of the ThumbEE instruction set,[132] and Armv8 removes support for ThumbEE.
VFP (Vector Floating Point) technology is afloating-point unit (FPU) coprocessor extension to the ARM architecture[133] (implemented differently in Armv8 – coprocessors not defined there). It provides low-costsingle-precision anddouble-precision floating-point computation fully compliant with theANSI/IEEE Std 754-1985 Standard for Binary Floating-Point Arithmetic. VFP provides floating-point computation suitable for a wide spectrum of applications such as PDAs, smartphones, voice compression and decompression, three-dimensional graphics and digital audio, printers, set-top boxes, and automotive applications. The VFP architecture was intended to support execution of short "vector mode" instructions but these operated on each vector element sequentially and thus did not offer the performance of truesingle instruction, multiple data (SIMD) vector parallelism. This vector mode was therefore removed shortly after its introduction,[134] to be replaced with the much more powerful Advanced SIMD, also namedNeon.
Some devices such as the ARM Cortex-A8 have a cut-downVFPLite module instead of a full VFP module, and require roughly ten times more clock cycles per float operation.[135] Pre-Armv8 architecture implemented floating-point/SIMD with the coprocessor interface. Other floating-point and/or SIMD units found in ARM-based processors using the coprocessor interface includeFPA, FPE,iwMMXt, some of which were implemented in software by trapping but could have been implemented in hardware. They provide some of the same functionality as VFP but are notopcode-compatible with it. FPA10 also providesextended precision, but implements correct rounding (required by IEEE 754) only in single precision.[136]
InDebianLinux and derivatives such asUbuntu andLinux Mint,armhf (ARM hard float) refers to the ARMv7 architecture including the additional VFP3-D16 floating-point hardware extension (and Thumb-2) above. Software packages and cross-compiler tools use the armhf vs. arm/armel suffixes to differentiate.[138]
TheAdvanced SIMD extension (also known asNeon or "MPE" Media Processing Engine) is a combined 64- and128-bit SIMD instruction set that provides standardised acceleration for media and signal processing applications. Neon is included in all Cortex-A8 devices, but is optional in Cortex-A9 devices.[139] Neon can execute MP3 audio decoding on CPUs running at 10 MHz, and can run theGSMadaptive multi-rate (AMR) speech codec at 13 MHz. It features a comprehensive instruction set, separate register files, and independent execution hardware.[140] Neon supports 8-, 16-, 32-, and 64-bit integer and single-precision (32-bit) floating-point data and SIMD operations for handling audio and video processing as well as graphics and gaming processing. In Neon, the SIMD supports up to 16 operations at the same time. The Neon hardware shares the same floating-point registers as used in VFP. Devices such as the ARM Cortex-A8 and Cortex-A9 support 128-bit vectors, but will execute with 64 bits at a time,[135] whereas newer Cortex-A15 devices can execute 128 bits at a time.[141][142]
A quirk of Neon in Armv7 devices is that it flushes allsubnormal numbers to zero, and as a result theGCC compiler will not use it unless-funsafe-math-optimizations, which allows losing denormals, is turned on. "Enhanced" Neon defined since Armv8 does not have this quirk, but as ofGCC 8.2 the same flag is still required to enable Neon instructions.[143] On the other hand, GCC does consider Neon safe on AArch64 for Armv8.
ProjectNe10 is ARM's first open-source project (from its inception; while they acquired an older project, now namedMbed TLS). The Ne10 library is a set of common, useful functions written in both Neon and C (for compatibility). The library was created to allow developers to use Neon optimisations without learning Neon, but it also serves as a set of highly optimised Neon intrinsic and assembly code examples for common DSP, arithmetic, and image processing routines. The source code is available on GitHub.[144]
Helium is the M-Profile Vector Extension (MVE). It adds more than 150 scalar and vector instructions.[145]
The Security Extensions, marketed as TrustZone Technology, is in ARMv6KZ and later application profile architectures. It provides a low-cost alternative to adding another dedicated security core to an SoC, by providing two virtual processors backed by hardware based access control. This lets the application core switch between two states, referred to asworlds (to reduce confusion with other names for capability domains), to prevent information leaking from the more trusted world to the less trusted world. This world switch is generally orthogonal to all other capabilities of the processor, thus each world can operate independently of the other while using the same core. Memory and peripherals are then made aware of the operating world of the core and may use this to provide access control to secrets and code on the device.[146]
Typically, a rich operating system is run in the less trusted world, with smaller security-specialised code in the more trusted world, aiming to reduce theattack surface. Typical applications includeDRM functionality for controlling the use of media on ARM-based devices,[147] and preventing any unapproved use of the device.
In practice, since the specific implementation details of proprietary TrustZone implementations have not been publicly disclosed for review, it is unclear what level of assurance is provided for a giventhreat model, but they are not immune from attack.[148][149]
Open Virtualization[150] is an open source implementation of the trusted world architecture for TrustZone.
AMD has licensed and incorporated TrustZone technology into itsSecure Processor Technology.[151] AMD'sAPUs include a Cortex-A5 processor for handling secure processing, which is enabled in some, but not all products.[152][153][154] In fact, the Cortex-A5 TrustZone core had been included in earlier AMD products, but was not enabled due to time constraints.[153]
Samsung Knox uses TrustZone for purposes such as detecting modifications to the kernel, storing certificates and attestating keys.[155]
The Security Extension, marketed as TrustZone for Armv8-M Technology, was introduced in the Armv8-M architecture. While containing similar concepts to TrustZone for Armv8-A, it has a different architectural design, as world switching is performed using branch instructions instead of using exceptions. It also supports safe interleaved interrupt handling from either world regardless of the current security state. Together these features provide low latency calls to the secure world and responsive interrupt handling. ARM provides a reference stack of secure world code in the form of Trusted Firmware for M andPSA Certified.
As of ARMv6, the ARM architecture supportsno-execute page protection, which is referred to asXN, foreXecute Never.[156]
The Large Physical Address Extension (LPAE), which extends the physical address size from 32 bits to 40 bits, was added to the Armv7-A architecture in 2011.[157]
The physical address size may be even larger in processors based on the 64-bit (Armv8-A) architecture. For example, it is 44 bits in Cortex-A75 and Cortex-A65AE.[158]
TheArmv8-R andArmv8-M architectures, announced after the Armv8-A architecture, share some features with Armv8-A. However, Armv8-M does not include any 64-bit AArch64 instructions, and Armv8-R originally did not include any AArch64 instructions; those instructions were added toArmv8-R later.
The Armv8.1-M architecture, announced in February 2019, is an enhancement of the Armv8-M architecture. It brings new features including:
Announced in October 2011,[13]Armv8-A (often called ARMv8 while the Armv8-R is also available) represents a fundamental change to the ARM architecture. It supports twoExecution states: a 64-bit state namedAArch64 and a 32-bit state namedAArch32. In the AArch64 state, a new 64-bitA64 instruction set is supported; in the AArch32 state, two instruction sets are supported: the original 32-bit instruction set, namedA32, and the 32-bit Thumb-2 instruction set, namedT32. AArch32 providesuser-space compatibility with Armv7-A. The processor state can change on an Exception level change; this allows 32-bit applications to be executed in AArch32 state under a 64-bit OS whose kernel executes in AArch64 state, and allows a 32-bit OS to run in AArch32 state under the control of a 64-bithypervisor running in AArch64 state.[1] ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012.[73] Apple was the first to release an Armv8-A compatible core in a consumer product (Apple A7 iniPhone 5S).AppliedMicro, using anFPGA, was the first to demo Armv8-A.[159] The first Armv8-ASoC fromSamsung is the Exynos 5433 used in theGalaxy Note 4, which features two clusters of four Cortex-A57 and Cortex-A53 cores in abig.LITTLE configuration; but it will run only in AArch32 mode.[160]
To both AArch32 and AArch64, Armv8-A makes VFPv3/v4 and advanced SIMD (Neon) standard. It also adds cryptography instructions supportingAES,SHA-1/SHA-256 andfinite field arithmetic.[161] AArch64 was introduced in Armv8-A and its subsequent revision. AArch64 is not included in the 32-bit Armv8-R and Armv8-M architectures.
An ARMv8-A processor can support one or both of AArch32 and AArch64; it may support AArch32 and AArch64 at lower Exception levels and only AArch64 at higher Exception levels.[162] For example, the ARM Cortex-A32 supports only AArch32,[163] theARM Cortex-A34 supports only AArch64,[164] and theARM Cortex-A72 supports both AArch64 and AArch32.[165] An ARMv9-A processor must support AArch64 at all Exception levels, and may support AArch32 at EL0.[162]
Optional AArch64 support was added to the Armv8-R profile, with the first ARM core implementing it being the Cortex-R82.[166] It adds the A64 instruction set.
Announced in March 2021, the updated architecture places a focus on secure execution andcompartmentalisation.[167][168]
Arm SystemReady is a compliance program that helps ensure the interoperability of an operating system on Arm-based hardware from datacenter servers to industrial edge and IoT devices. The key building blocks of the program are the specifications for minimum hardware and firmware requirements that the operating systems and hypervisors can rely upon. These specifications are:[169]
These specifications are co-developed byArm and its partners in the System Architecture Advisory Committee (SystemArchAC).
Architecture Compliance Suite (ACS) is the test tools that help to check the compliance of these specifications. The Arm SystemReady Requirements Specification documents the requirements of the certifications.[174]
This program was introduced byArm in 2020 at the firstDevSummit event. Its predecessor Arm ServerReady was introduced in 2018 at the Arm TechCon event. This program currently includes two bands:
PSA Certified, formerly named Platform Security Architecture, is an architecture-agnostic security framework and evaluation scheme. It is intended to help secureInternet of things (IoT) devices built on system-on-a-chip (SoC) processors.[177] It was introduced to increase security where a fulltrusted execution environment is too large or complex.[178]
The architecture was introduced byArm in 2017 at the annualTechCon event.[178][179] Although the scheme is architecture agnostic, it was first implemented on Arm Cortex-M processor cores intended for microcontroller use. PSA Certified includes freely available threat models and security analyses that demonstrate the process for deciding on security features in common IoT products.[180] It also provides freely downloadable application programming interface (API) packages, architectural specifications, open-source firmware implementations, and related test suites.[181]
Following the development of the architecture security framework in 2017, thePSA Certified assurance scheme launched two years later at Embedded World in 2019.[182] PSA Certified offers a multi-level security evaluation scheme for chip vendors, OS providers and IoT device makers.[183] The Embedded World presentation introduced chip vendors to Level 1 Certification. A draft of Level 2 protection was presented at the same time.[184] Level 2 certification became a usable standard in February 2020.[185]
The certification was created by PSA Joint Stakeholders to enable a security-by-design approach for a diverse set of IoT products. PSA Certified specifications are implementation and architecture agnostic, as a result they can be applied to any chip, software or device.[186][184] The certification also removes industry fragmentation forIoT product manufacturers and developers.[187]
The first 32-bit ARM-based personal computer, theAcorn Archimedes, was originally intended to run an ambitious operating system calledARX. The machines shipped withRISC OS, which was also used on later ARM-based systems from Acorn and other vendors. Some early Acorn machines were also able to run aUnix port calledRISC iX. (Neither is to be confused withRISC/os, a contemporary Unix variant for the MIPS architecture.)
The 32-bit ARM architecture is supported by a large number ofembedded andreal-time operating systems, including:
As of March 2024, the 32-bit ARM architecture used to be the primary hardware environment for most mobile device operating systems such as the following but many of these platforms such as Android and Apple iOS have evolved to the 64-bit ARM architecture:
Formerly, but now discontinued:
The 32-bit ARM architecture is supported by RISC OS and by multipleUnix-like operating systems including:
Windows applications recompiled for ARM and linked with Winelib, from theWine project, can run on 32-bit or 64-bit ARM in Linux, FreeBSD, or other compatible operating systems.[216][217] x86 binaries, e.g. when not specially compiled for ARM, have been demonstrated on ARM usingQEMU with Wine (on Linux and more),[citation needed] but do not work at full speed or same capability as with Winelib.
the cumulative deployment of 100 billion chips, half of which shipped in the last four years. [..] why not a trillion or more? That is our target, seeing a trillion connected devices deployed over the next two decades.
ARM started as a branch of Acorn Computer in Cambridge, England, with the formation of a joint venture between Acorn, Apple and VLSI Technology. A team of twelve employees produced the design of the first ARM microprocessor between 1983 and 1985.
Apple has invested about $3 million (roughly 1.5 million pounds) for a 30% interest in the company, dubbed Advanced Risc Machines Ltd. (ARM) [...]
ARMv8 SVE (Scalable Vector Extension) chip, which uses 512bit floating point.
can execute two-threads in parallel on each cycle. Each thread can be at different exception levels and run different operating systems.
In relation to IEEE 754-1985, the FPA achieves conformance in single-precision arithmetic [...] Occasionally, double- and extended-precision multiplications may be produced with an error of 1 or 2 units in the least significant place of the mantissa.
APX and XN (execute never) bits have been added in VMSAv6 [Virtual Memory System Architecture]
This new version of Windows 10 is Microsoft's first 64-bit ARM operating system. It'll run x86 and 32-bit ARM applications from the Store, and in due course, 64-bit ARM applications. However, Microsoft hasn't yet finalised its 64-bit ARM SDK. Many pieces are in place (there's a 64-bit ARM compiler, for example), but the company isn't yet taking 64-bit ARM applications submitted to the Store, and there aren't any 64-bit ARM desktop applications either.
, ARM Ltd.
