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Advanced Synchronization Facility (ASF) is a proposed extension to thex86-64instruction set architecture that adds hardwaretransactional memory support. It was introduced byAMD; the latest specification was dated March 2009.[1] As of October 2013[update], it was still in the proposal stage.[2] No releasedmicroprocessors implement the extension.
ASF provides the capability to start, end and abort transactional execution and to markCPUcache lines for protected memory access in transactional code regions. It contains four new instructions—SPECULATE,COMMIT,ABORT andRELEASE—and turns the otherwise invalidLOCK-prefixedMOVx,PREFETCH andPREFETCHW instructions into valid ones inside transactional code regions. Up to 256 levels of nested transactional code regions is supported.
TheSPECULATE andCOMMIT instructions mark the start and end of a transactional code region. Inside transactional code regions, theLOCK-prefixedMOVx reg/xmm, mem,PREFETCH andPREFETCHW instructions can mark up to four cache lines for protected memory access. Accesses from other processor cores to the protected cache lines result in exceptions, which in turn cause transaction aborts. Stores to protected cache lines must be performed using theLOCK MOVx mem, reg/imm/xmm instructions. Marked cache lines can be released from protection with theRELEASE instruction. Transaction aborts generated by hardware or explicitly requested through theABORT instruction rolls back modifications to the protected cache lines and restarts execution from the instruction following the top-levelSPECULATE instruction.
