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The ArmAdvanced Microcontroller Bus Architecture (AMBA) is an open-standard, on-chip interconnect specification for the connection and management offunctional blocks insystem-on-a-chip (SoC) designs. It facilitates development of multi-processor designs with large numbers of controllers and components with abus architecture. Since its inception, the scope of AMBA has, despite its name, gone far beyond microcontroller devices. Today, AMBA is widely used on a range ofASIC and SoC parts including applications processors used in modern portable mobile devices likesmartphones. AMBA is a registered trademark ofArm Ltd.[1]
AMBA was introduced by Arm in 1996. The first AMBA buses were the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). In its second version, AMBA 2 in 1999, Arm added AMBA High-performance Bus (AHB) that is a single clock-edge protocol. In 2003, Arm introduced the third generation, AMBA 3, including Advanced eXtensible Interface (AXI) to reach even higher performance interconnect and the Advanced Trace Bus (ATB) as part of the CoreSight on-chip debug and trace solution. In 2010 the AMBA 4 specifications were introduced starting with AMBA 4 AXI4, then in 2011[2] extending system-wide coherency with AMBA 4 AXI Coherency Extensions (ACE). In 2013[3] the AMBA 5 Coherent Hub Interface (CHI) specification was introduced, with a re-designed high-speed transport layer and features designed to reduce congestion. These protocols are today thede facto standard for embedded processor bus architectures because they are well documented and can be used without royalties.
An important aspect of an SoC is not only which components or blocks it houses, but also how they interconnect. AMBA is a solution for the blocks to interface with each other.
The objective of the AMBA specification is to:
The AMBA specification defines an on-chip communications standard for designing high-performance embedded microcontrollers. It is supported byArm Limited with wide cross-industry participation.
TheAMBA 5 specification defines the following buses/interfaces:
TheAMBA 4 specification defines following buses/interfaces:
AMBA 3 specification defines four buses/interfaces:
AMBA 2 specification defines three buses/interfaces:
AMBA specification (First version) defines two buses/interfaces:
The timing aspects and thevoltage levels on the bus are not dictated by the specifications.
ACE, defined as part of the AMBA 4 specification, extends AXI with additional signalling introducing system wide coherency.[4] This system coherency allows multiple processors to share memory and enables technology like Arm'sbig.LITTLE processing. TheACE-Lite protocol enables one-way coherency, also known as I/O coherency; for example, a network interface that can read from the caches of a fully coherent ACE processor.
AXI, the third generation of AMBA interface defined in the AMBA 3 specification, is targeted at high performance, high clock frequency system designs and includes features that make it suitable for high speed sub-micrometer interconnect:
AHB is a bus protocol introduced in Advanced Microcontroller Bus Architecture version 2 published byArm Ltd company.
In addition to previous release, it has the following features:
A simple transaction on the AHB consists of an address phase and a subsequent data phase (without wait states: only two bus-cycles). Access to the target device is controlled through aMUX (non-tristate), thereby admitting bus-access to one bus-master at a time.
AHB-Lite is a subset of AHB formally defined in the AMBA 3 standard. This subset simplifies the design for a bus with a single master.
APB is designed for low bandwidth control accesses, for example register interfaces on system peripherals. This bus has an address and data phase similar to AHB, but a much reduced, low complexity signal list (for example no bursts).Furthermore, it is an interface designed for a low frequency system with a low bit width (32 bits).
A family of synthesizable intellectual property (IP) coresAMBA Products is licensable fromArm Limited that implement a digital bus in an SoC for the efficient moving and storing of data using the AMBA protocol specifications. The AMBA family includes AMBA Network Interconnect (CoreLink NIC-400), Cache Coherent Interconnect (CoreLink CCI-500),SDRAM memory controllers (CoreLink DMC-400),DMA controllers (CoreLink DMA-230, DMA-330), level 2 cache controllers (L2C-310), etc.
A number of manufacturers utilize AMBA buses for non-ARM designs. As an exampleInfineon uses an AMBA bus for the ADM5120 SoC based on theMIPS architecture.
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Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.  Category | |