Theaddress generation unit (AGU), sometimes also calledaddress computation unit (ACU),[1] is anexecution unit insidecentral processing units (CPUs) that calculatesaddresses used by the CPU to accessmain memory. By having address calculations handled by separate circuitry that operates in parallel with the rest of the CPU, the number ofCPU cycles required for executing variousmachine instructions can be reduced, bringing performance improvements.[2][3]
While performing various operations, CPUs need to calculate memory addresses required for fetching data from the memory; for example, in-memory positions ofarray elements must be calculated before the CPU can fetch the data from actual memory locations. Those address-generation calculations involve differentinteger arithmetic operations, such as addition, subtraction,modulo operations, orbit shifts. Often, calculating a memory address involves more than one general-purpose machine instruction, which do not necessarilydecode and execute quickly. By incorporating an AGU into a CPU design, together with introducing specialized instructions that use the AGU, various address-generation calculations can be offloaded from the rest of the CPU, and can often be executed quickly in a single CPU cycle.[2][3]
Capabilities of an AGU depend on a particular CPU and itsarchitecture. Thus, some AGUs implement and expose more address-calculation operations, while some also include more advanced specialized instructions that can operate on multipleoperands at a time.[2][3] Furthermore, some CPU architectures include multiple AGUs so more than one address-calculation operation can be executed simultaneously, bringing further performance improvements by capitalizing on thesuperscalar nature of advanced CPU designs. For example,Intel incorporates multiple AGUs into itsSandy Bridge andHaswellmicroarchitectures, which increase bandwidth of the CPU memory subsystem by allowing multiple memory-access instructions to be executed in parallel.[4][5][6]
