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| General information | |
|---|---|
| Launched | 2020 |
| Designed by | ARM Ltd. |
| Performance | |
| Max.CPUclock rate | to 3.0 GHz in phones and 3.3 GHz in tablets/laptops |
| Address width | 40-bit |
| Physical specifications | |
| Cores |
|
| Cache | |
| L1cache | 128KiB(64 KiBI-cache with parity,64 KiBD-cache) per core |
| L2 cache | 512–1024 KiB per core |
| L3 cache | 512 KiB – 8 MiB(optional) |
| Architecture and classification | |
| Microarchitecture | ARM Cortex-X1 |
| Instruction set | ARMv8-A: A64, A32, and T32(at the EL0 only) |
| Extensions | |
| Products, models, variants | |
| Product code name |
|
| Variant | |
| History | |
| Successor | ARM Cortex-X2 |
TheARM Cortex-X1 is acentral processing unit implementing theARMv8.2-A 64-bitinstruction set designed byARM Holdings'Austin design centre as part of ARM's Cortex-X Custom (CXC) program.[1][2]
The Cortex-X1 design is based on theARM Cortex-A78, but redesigned for purely performance instead of a balance of performance, power, and area (PPA).[1]
The Cortex-X1 is a 5-wide decodeout-of-ordersuperscalar design with a 3K macro-OP (MOPs) cache. It can fetch 5 instructions and 8 MOPs per cycle, and rename and dispatch 8 MOPs, and 16 μOPs per cycle. The out-of-order window size has been increased to 224 entries. The backend has 15 execution ports with a pipeline depth of 13 stages and the execution latencies consists of 10 stages. It also features 4x128b SIMD units.[3][4][5][6]
ARM claims the Cortex-X1 offers 30% faster integer and 100% faster machine learning performance than theARM Cortex-A77.[3][4][5][6]
The Cortex-X1 supportsARM's DynamIQ technology, expected to be used as high-performance cores when used in combination with theARM Cortex-A78 mid andARM Cortex-A55 little cores.[1][2]
The Cortex-X1 is available asSIP core to partners of their Cortex-X Custom (CXC) program, and its design makes it suitable for integration with other SIP cores (e.g.GPU,display controller,DSP,image processor, etc.) into onedie constituting asystem on a chip (SoC).[1][2]
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