| General information | |
|---|---|
| Launched | 2020 |
| Designed by | ARM Ltd. |
| Performance | |
| Max.CPUclock rate | 2.4 GHz to 3.0 GHz in phones and 3.3 GHz in tablets/laptops |
| Cache | |
| L1cache | 32–64 KB (parity) 32kb L1 Instruction cache and 32kb L1 Data cache.or 64kb L1 Instruction cache and 64kb L1 Data cache. |
| L2 cache | 256–512 (private L2 ECC)KiB |
| L3 cache | Optional, 512 KB to 4 MB (A78, A78AE) Optional, 512 KB to 8 MB (A78C) |
| Architecture and classification | |
| Microarchitecture | ARM Cortex-A78 |
| Instruction set | ARMv8-A |
| Extensions | |
| Physical specifications | |
| Cores |
|
| Products, models, variants | |
| Product code name |
|
| Variant | |
| History | |
| Predecessor | ARM Cortex-A77 |
| Successor | ARM Cortex-A710 |
TheARM Cortex-A78 is acentral processing unit implementing theARMv8.2-A 64-bitinstruction setdesigned byARM Ltd.'sAustin centre.[failed verification][1]
The ARM Cortex-A78 is the successor to theARM Cortex-A77. It can be paired with theARM Cortex-X1 and/orARM Cortex-A55 CPUs in aDynamIQ configuration to deliver both performance and efficiency. The processor also claims as much as 50% energy savings over its predecessor.[2]
The Cortex-A78 is a 4-wide decodeout-of-ordersuperscalar design with a 1.5K macro-OP (MOPs) cache. It can fetch 4 instructions and 6 Mops per cycle, and rename and dispatch 6 Mops, and 12μops per cycle. The out-of-order window size is 160 entries and the backend has 13 execution ports with a pipeline depth of 14 stages, and the execution latencies consist of 10 stages.[2][3][4]
The processor is built on a standard Cortex-A roadmap and offers a 2.1 GHz (5 nm) chipset which makes it better than its predecessor in the following ways:
There is also extended scalability with extra support from Dynamic Shared Unit forDynamIQ on the chipset. A smaller 32 KB L1cache from the 64 KB L1 cache configuration is optional. To offset this smaller L1 memory, thebranch predictor is better at covering irregular search patterns and is capable of following two taken branches per cycle, which results in fewer L1 cache misses and helps hide pipeline bubbles to keep the core well supplied. The pipeline is one cycle longer compared to the A77, which ensures that the A78 hits aclock frequency target of around 3 GHz. The A78 is a 6 instruction per cycle design.
ARM also introduced a second integer multiply unit in the execution unit and an additional load Address Generation Unit (AGU) to increase both the data load and bandwidth by 50%. Other optimizations of the chipset include fused instructions[5] and efficiency improvements to instruction schedulers,register renaming structures, and there-order buffer.
L2 cache is available up to 512 KB and has double the bandwidth to maximize the performance, while the shared L3 cache is available up to 4 MB, double that of previous generations. A Dynamic Shared Unit (DSU) also allows for an 8 MB configuration with theARM Cortex-X1.[3][4][2][6]
The Cortex-A78C is targeted for productivity and gaming applications, it increases the max core support from 4 to 8 cores and from 4MB to 8MB of L3 cache.[7]
The Cortex-A78AE is targeted for security/safety applications.[8]
The Cortex-A78 is available as aSIP core to licensees whilst its design makes it suitable for integration with other SIP cores (e.g.GPU,display controller,DSP,image processor, etc.) into onedie constituting asystem on a chip (SoC).[citation needed]
The Cortex-A78 was first used in SamsungExynos 2100 SoC, introduced in November and December 2020 respectively.[9][10] The customKryo 680 Gold core used in theSnapdragon 888[broken anchor] SoC is based on the Cortex-A78 microarchitecture.[11][12] The Cortex-A78 is also used in theMediaTek Dimensity 1200 and 8000 series. The device is also used inNvidia'sBlueField-3 and 3XDPUs, and in the HiSiliconKirin 9000s, released in August 2023.
The Cortex-A78C is used in Nvidia's T239 SoC that powers theNintendo Switch 2.[13]