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| General information | |
|---|---|
| Designed by | ARM Holdings |
| Architecture and classification | |
| Instruction set | ARM (32-bit), Thumb (16-bit), Thumb-2 (32-bit) (ARMv6, ARMv6T2, ARMv6Z, ARMv6K) |
ARM11 is a group of32-bitRISCARM processor cores licensed byARM Holdings.[1] The ARM11 core family consists of ARM1136J(F)-S, ARM1156T2(F)-S, ARM1176JZ(F)-S, and ARM11MPCore. Since ARM11 cores were released from2002 to 2005, and no longer recommended for new IC designs, newer alternatives areARM Cortex-A andARM Cortex-R cores.[1]
| Announced | |
|---|---|
| Year | Core |
| 2002 | ARM1136J(F)-S |
| 2003 | ARM1156T2(F)-S |
| 2003 | ARM1176JZ(F)-S |
| 2005 | ARM11MPCore |
The ARM11 product family (announced 29 April 2002) introduced theARMv6 architectural additions which had been announced in October 2001. These includeSIMD media instructions,multiprocessor support,exclusive loads and stores instructions[2] and a new cache architecture. The implementation included a significantly improved instruction processing pipeline, compared to previousARM9 orARM10 families, and is used insmartphones fromApple,Nokia, and others. The initial ARM11 core (ARM1136) was released to licensees in October 2002.
The ARM11 family are currently the only ARMv6-architecture cores. There are, however, ARMv6-M cores (Cortex-M0 and Cortex-M1), addressingmicrocontroller applications;[3] ARM11 cores target more demanding applications.
In terms of instruction set, ARM11 builds on the precedingARM9 generation. It incorporates all ARM926EJ-S features and adds the ARMv6 instructions for media support (SIMD) and accelerating IRQ response.
Microarchitecture improvements in ARM11 cores[4] include:
JTAG debug support (for halting, stepping, breakpoints, and watchpoints) was simplified. The EmbeddedICE module was replaced with an interface which became part of the ARMv7 architecture. The hardware tracing modules (ETM and ETB) are compatible, but updated, versions of those used in the ARM9. In particular, trace semantics were updated to address parallel instruction execution and data transfers.
ARM makes an effort to promote recommendedVerilog coding styles and techniques. This ensures semantically rigorous designs, preserving identical semantics throughout the chip design flow, which included extensive use offormal verification techniques. Without such attention, integrating an ARM11 with third-party designs could risk exposing hard-to-find latent bugs. Due to ARM cores being integrated into many different designs, using a variety oflogic synthesis tools and chip manufacturing processes, the impact of itsregister-transfer level (RTL) quality is magnified many times.[5] The ARM11 generation focused more on synthesis than previous generations, making such concerns more of an issue.
There are four ARM11 cores:
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