Aneural processing unit (NPU), also known as anAI accelerator ordeep learning processor, is a class of specializedhardware accelerator[1] or computer system[2][3] designed to accelerateartificial intelligence (AI) andmachine learning applications, includingartificial neural networks andcomputer vision.
Their purpose is either to efficiently execute already trained AI models (inference) or to train AI models. Their applications includealgorithms forrobotics,Internet of things, anddata-intensive or sensor-driven tasks.[4] They are oftenmanycore orspatial designs and focus onlow-precision arithmetic, noveldataflow architectures, orin-memory computing capability. As of 2024[update], a widely used datacenter-grade AIintegrated circuit chip, theNvidiaH100 GPU,contains tens of billions ofMOSFETs.[5]
AI accelerators are used in mobile devices such as AppleiPhones, AMDAI engines[6] in Versal and NPUs,Huawei, andGoogle Pixel smartphones,[7] and seen in manyApple silicon,Qualcomm,Samsung, andGoogle Tensor smartphone processors.[8]
It is more recently (circa 2022) added to computer processors fromIntel,[9]AMD,[10] and Apple silicon.[11] All models of IntelMeteor Lake processors have a built-inversatile processor unit (VPU) for acceleratinginference for computer vision and deep learning.[12]
On consumer devices, the NPU is intended to be small, power-efficient, but reasonably fast when used to run small models. To do this they are designed to support low-bitwidth operations using data types such as INT4, INT8,FP8, andFP16. A common metric is trillions of operations per second (TOPS). Although TOPS does not explicitly specify the kind of operations, it is typically INT8 additions and multiplications.[13]
Accelerators are used incloud computing servers: e.g.,tensor processing units (TPU) forGoogle Cloud Platform,[14] andTrainium andInferentia chips forAmazon Web Services.[15] Many vendor-specific terms exist for devices in this category, and it is anemerging technology without adominant design.
Since the late 2010s,graphics processing units designed by companies such asNvidia andAMD often include AI-specific hardware in the form of dedicated functional units for low-precisionmatrix-multiplication operations. These GPUs are commonly used as AI accelerators, both fortraining andinference.[16]
Although NPUs are tailored for low-precision (e.g. FP16, INT8)matrix multiplication operations, they can be used to emulate higher-precision matrix multiplications in scientific computing. As modern GPUs place much focus on making the NPU part fast, using emulated FP64 (Ozaki scheme) on NPUs can potentially outperform native FP64: this has been demonstrated using FP16-emulated FP64 on NVIDIA TITAN RTX and using INT8-emulated FP64 on NVIDIA consumer GPUs and the A100 GPU. (Consumer GPUs are especially benefitted by this scheme as they have small amounts of FP64 hardware capacity, showing a 6× speedup.)[17] Since CUDA Toolkit 13.0 Update 2, cuBLAS automatically uses INT8-emulated FP64 matrix multiplication of the equivalent precision if it's faster than native. This is in addition to the FP16-emulated FP32 feature introduced in version 12.9.[18]
An operating system or a higher-level library may provideapplication programming interfaces such asTensorFlow Lite with LiteRT Next (Android) or CoreML (iOS, macOS). Formats such asONNX are used to represent trained neural networks.
Consumer CPU-integrated NPUs are accessible through vendor-specific APIs. AMD (Ryzen AI), Intel (OpenVINO), Apple silicon (CoreML),[a] and Qualcomm (SNPE) each have their own APIs, which can be built upon by a higher-level library.
GPUs generally use existingGPGPU pipelines such asCUDA andOpenCL adapted for lower precisions and specialized matrix-multiplication operations.Vulkan is also being used. Custom-built systems such as the GoogleTPU use private interfaces.
There are a large number of separate underlying acceleration APIs and compilers/runtimes in use in the AI field, causing a great increase in software development effort due to the many combinations involved. As of 2025, the open standard organizationKhronos Group is pursuing standardization of AI-related interfaces to reduce the amount of work needed. Khronos is working on three separate fronts: expansion of data types and intrinsic operations in OpenCL and Vulkan, inclusion of compute graphs inSPIR-V, and aNNEF/SkriptND file format for describing a neural network.[19]