 | |
| General information | |
|---|---|
| Launched | 1987 |
| Designed by | Motorola |
| Performance | |
| Max.CPUclock rate | 16 MHz to 50 MHz |
| Data width | 32 bits |
| Address width | 32 bits |
| Physical specifications | |
| Transistors |
|
| Package | |
| Cache | |
| L1cache | 256 bytes each for instruction and data, 16 lines of 4 entries of 4 bytes each, direct mapped[1][2] |
| Architecture and classification | |
| Instruction set | Motorola 68000 series |
| Products, models, variants | |
| Variant |
|
| History | |
| Predecessor | Motorola 68020 |
| Successor | Motorola 68040 |
TheMotorola 68030 ("sixty-eight-oh-thirty") is a32-bit microprocessor in theMotorola 68000 family. It was released in 1987. The 68030 was the successor to theMotorola 68020, and was followed by theMotorola 68040. In keeping with generalMotorola naming, this CPU is often referred to as the 030 (pronouncedoh-three-oh oroh-thirty).
The 68030 is essentially a 68020 with amemory management unit (MMU) and instruction and data caches of 256bytes each. It added aburst mode for the caches, where fourlongwords can be loaded into the cache in a single operation. The MMU was mostly compatible with the external68851 that would be used with the 68020,[3] but being internal allowed it to access memory one cycle faster than a 68020/68851 combo. The 68030 did not include a built-infloating-point unit (FPU), and was generally used with the68881 and the faster68882. The addition of the FPU was a major design note of the subsequent 68040. The 68030 typically increases performance by ≈5% over the 68020, while reducing power draw by ≈25%.[citation needed]
The 68030 features 273,000 transistors. A lower-cost version was also released, the Motorola 68EC030, lacking the on-chip MMU. It was commonly available in both 132-pinQFP and 128-pinPGA packages. The poorer thermal characteristics of the QFP package limited that variant to 33 MHz; the PGA 68030s included 40 MHz and 50 MHz versions. There was also a small supply of QFP packaged EC variants.
The 68030 can be used with the 68020 bus, in which case its performance is similar to 68020 that it was derived from. However, the 68030 provides an additional synchronous bus interface which, if used, accelerates memory accesses up to 33% compared to an equally clocked 68020. The finer manufacturing process allowed Motorola to scale the full-version processor to 50 MHz. The EC variety topped out at 40 MHz.
The 68030 was used in many models of theAppleMacintosh II andCommodore Amiga series ofpersonal computers,NeXT Computer, laterAlpha Microsystems multiuser systems, and some descendants of theAtari ST line such as theAtari TT and theAtari Falcon. It was also used in Unixworkstations such as theSun MicrosystemsSun-3x line of desktop workstations (the earlier "sun3" used a 68020),Apollo Computer'sDN3500 and DN4500 workstations,[4]laser printers and the Nortel NetworksDMS-100 telephone central office switch. More recently[when?], the 68030 core has also been adapted byFreescale into amicrocontroller for embedded applications.
LeCroy has used the 68EC030 in certain models of their 9300 Series digital oscilloscopes including “C” suffix models[5]: 87-88 and high performance 9300 Series models,[5] along with the Mega Waveform Processing hardware option for 68020-based 9300 Series models.[5]
The 68EC030 is a low cost version of the 68030, the difference between the two being that the 68EC030 omits the on-chipmemory management unit (MMU) and is thus essentially an upgraded 68020.
The 68EC030 was used as the CPU for the low-cost model of theAmiga 4000, and on a number of CPU accelerator cards for theCommodore Amiga line of computers. It was also used in theCisco Systems2500 Series router, a small-to-medium enterprise computer internetworking appliance. Additionally it was also used as the primary processor in a number ofAlpha Microsystems Eagle mini-computers.
The 50 MHz speed is exclusive to the ceramicPGA package, the plastic 68030 stopped at 40 MHz.
| CPUclock rate | 16, 20, 25, 33, 40, 50 MHz, except for MC68EC030 available in 25 and 40 MHz | [1] |
| Internalsplit-cache modified Harvard architecture | [1] | |
| Address bus | 32 bit | [6] |
| Data bus | 32 bit | [6] |
| Cache | 256 bytes each for instruction and data, 16 lines of 4 entries of 4 bytes each, direct mapped | [1][2] |
| dynamic bus sizing | [1] | |
| burst memory interface | [1] | |
| Performance | 18 MIPS @ 50 MHz | [1] |
Neither the PMMU nor the 68030 MMU constitutes a proper superset of the other. The PMMU has instructions and registers not found in the 68030 MMU, while the latter has registers not on the PMMU. However, in a typical Unix implementation little work would needed [sic] to port PMMU specific code to the 68030.
