 PDIP40 package | |
| General information | |
|---|---|
| Launched | 1985; 40 years ago (1985) |
| Common manufacturer |
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| Performance | |
| Max.CPUclock rate | 1 MHz to 14 MHz |
| Data width |
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| Address width | 24 bits |
| Architecture and classification | |
| Instruction set | 6502 |
| Number of instructions | 92 |
| Physical specifications | |
| Packages | |
| Products, models, variants | |
| Variant |
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| History | |
| Predecessors |
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| Successor | WDC 65C832[1][2][3] (never released) |
TheW65C816S (also65C816 or65816) is a 16-bitmicroprocessor (MPU) developed and sold by theWestern Design Center (WDC). Introduced in 1985, the W65C816S is an enhanced version of theWDC 65C028-bit MPU, itself aCMOS enhancement of the venerableMOS Technology6502NMOS MPU. The 65C816 is the CPU for theApple IIGS and, in modified form, theSuper Nintendo Entertainment System.
The65 in the part's designation comes from its 65C02 compatibility mode, and the816 signifies that the MPU has selectable 8- and16-bitregister sizes. In addition to the availability of 16-bit registers, the W65C816S extendsmemory addressing to24 bits, supporting up to 16megabytes ofrandom-access memory. It has an enhanced instruction set and a 16-bitstack pointer, as well as several new electrical signals for improved system hardware management.
Atreset, the W65C816S starts in "emulation mode", meaning it substantially behaves as a 65C02. Thereafter, the W65C816S may be switched to "native mode" with a two instruction sequence, causing it to enable all enhanced features, yet still maintain a substantial degree ofbackward compatibility with most 65C02 software. However, unlike thePDIP40 version of the 65C02, which is apin-compatible replacement for its NMOS ancestor, the PDIP40 W65C816S is not pin-compatible with any other 6502 family MPU.
TheW65C802 or65802 is completely software-compatible with the 65C816 and it is also electrically-compatible with the 6502 and 65C02. Hence the 65C802 could be used as a drop-in replacement in most systems equipped with a 6502 or 65C02. However, the 65C802 cannot emit a 24-bit address, which limits it to a 64 KB address space. The 65C802 is no longer produced.
In 1981,Bill Mensch, founder andCEO of WDC, began development of the 65C02 with his production partners, primarilyRockwell Semiconductor andSynertek. The primary goal of the 65C02 effort was to move from the original 6502's NMOS process to the CMOS process, which would allow it to run at much lower power levels, somewhere between1⁄10 and1⁄20 at any given clock speed. Also desired was the ability to raise the maximum supported clock speed. The 65C02 design addressed chip errata present in the NMOS 6502 (e.g., the infamousJMP (<addr>) bug) and introduced new instructions and new addressing modes for some existing instructions.[4]
Development of the W65C816S commenced in 1982 after Mensch consulted withApple Computer on a new version of theApple II series ofpersonal computers that would, among other things, have improved graphics and sound. Apple wanted an MPU that would be software compatible with the 6502 then in use in the Apple II but with the ability to address more memory, and to load and store 16-bit words. The result was the 65C816, finished in March 1984, with samples provided to both Apple andAtari in the second half of the year and full release in 1985.[5] Mensch was aided during the design process by his sister Kathryn, who was responsible for part of the device's layout.
The same process also led to the 65C802, which was identical inside to the 65C816. Both were produced on the same fabrication lines and diverged only during the last metalization stages when the chip was being connected to the external pins. In the 65C802, those pins had the same layout as the original 6502, which allowed it to be used as a drop-in replacement while still allowing the 16-bit processing of the CPU to be used. However, as it used the original pinout it had only 16 addressing pins, and could therefore only access 64 KB of external memory.[6] Typically, when hardware manufacturers designed a project from the ground up, they used the 65C816 rather than the 65C802, resulting in the latter being withdrawn from production.
Apple subsequently integrated the 65C816 into theApple IIGS computer. The basic 65C816 design wassecond-sourced byVLSI Technology,[7]GTE,Sanyo and others from the mid-to-late 1980s to the early 1990s.
In the 1990s, both the 65C816 and 65C02 were converted to a fullystatic core, which made it possible to completely stop theprocessor's Ø2 clock without loss of register contents. This feature, along with the use ofasynchronous static RAM, made it possible to produce designs that used minimal power when in a standby state.
As of April 2024[update], the W65C816S is available from WDC in 40-pinPDIP,PLCC44, or 44-pinTQFP packaging, as anMCU through the W65C265,[8] and as IP cores forASIC integration[9][10] (for exampleWinbond's W55V9x series of TVEdutainmentICs[11]).
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WDC 65c816 features:
C),stack pointer (SP), andindex registers (X andY).DP).DB) and program bank (PB) registers, generating bits 16–23 of 24-bit code and data addresses. Separate program and data bank registers allow programsegmentation and 16 MB linear data addressing.VDA) and valid program address (VPA) control outputs for memory qualification, dualcache and cycle stealDMA implementation.VPB) control output to indicate when aninterrupt vector is being fetched.ABORTB) input and associated vector supports processor repairs of bus error conditions, such aspage faults and memory access violations.MVN andMVP), allowing rapid copying of data structures from one area ofRAM to another with minimal code.WAI) and Stop-the-Clock (STP) instructions furtherreduce power consumption, decreaseinterrupt latency and allow synchronization with external events.COP) instruction with associated vector supports co-processor configurations, e.g.,floating point processors.WDM) instruction for future two-byte opcodes and a link to future designs (WDM are the initials of W65C816S designerWilliam D. Mensch).The 65C816 has two operating modes: "emulation mode", in which the 16-bit operations are invisible—the index registers are forced to eight bits—and the chip appears to be very similar to the 6502, with the same cycle timings for the opcodes; and "native mode", which exposes all new features. The CPU automatically enters emulation mode when it is powered on or reset, which allows it to replace a 65(C)02, assuming one makes the required circuit changes to accommodate the different pin layout.[4]
The most obvious change to the 65C816 when running in native mode is the expansion of the various registers from 8-bit to 16-bit sizes. This enhancement affects the accumulator (A), theX andYindex registers, and thestack pointer (SP). It does not affect theprogram counter (PC), which has always been 16-bit.[12]
When running in native mode, two bits in the status register change their meaning. In the original 6502, bits 4 and 5 were not used, although bit 4 is referred to as the break (b) flag. In native mode, bit 4 becomes thex flag and bit 5 becomes them flag. These bits control whether or not theindex registers (x) and accumulator/memory (m) are 8-bit or 16-bit in size. Zeros in these bits set 16-bit sizes, ones set 8-bit sizes. These bits are locked at ones when the processor is powered on or reset, but become changeable when the processor is switched to native mode.[12]
In native mode operation, the accumulator and index registers may be set to 16- or 8-bit sizes at the programmer’s discretion by using theREP andSEP instructions to manipulate them andx status register bits. This feature gives the programmer the ability to perform operations on either word- and byte-size data. As the accumulator and index register sizes are independently settable, it is possible, for example, to have the accumulator set to eight bits and the index registers set to 16 bits, giving the programmer the ability to manipulate individual bytes over a 64KB range without having to perform pointer arithmetic.
When register sizes are set to 16 bits, a memory access will fetch or store two contiguous bytes at the rate of one byte per clock cycle. Hence a read-modify-write instruction, such asROR <addr>, when used while the accumulator is set to 16 bits, will affect two contiguous bytes of memory, not one and will consume more clock cycles than when the accumulator is set to eight bits. Similarly, all arithmetic and logical operations will be 16-bit operations.[13]
The other major change to the system while running in native mode is that the memory model is expanded to a 24-bit format from the original 16-bit format of the 6502. The 65c816 makes use of two 8-bit registers, the data bank register (DB) and the program bank register (PB), to set bits 16-23 of the address, effectively generating 24-bit addresses. In both cases, 'bank' refers to a contiguous 64 KB segment of memory that is bounded by the address range$xx0000–$xxFFFF, wherexx is the bank address, that is, bits 16-23 of the effective address. BothDB andPB are initialized to$00 at power-on or reset.[14]
During anopcode oroperand fetch cycle,PB is prepended to theprogram counter (PC) to form the 24-bit effective address. ShouldPC "wrap" (return to zero),PB will not be incremented. Hence a program is bounded by the limits of the bank in which it is executing. Implied by this memory model is that branch and subroutine targets must be in the same bank as the instruction making the branch or call, unless "long" jumps or subroutine calls are used to execute code in another bank. There is no programmatic means by whichPB can be directly changed.[15]
During a data fetch or store cycle,DB is prepended to a 16-bit data address to form the 24-bit effective address at which data will be accessed. This processor characteristic makes it possible to sanely execute 6502 or 65c02 code that uses 16-bit addresses to reference data elements. UnlikePB,DB can be changed under program control, something that might be done to access data beyond the limits of 16-bit addressing. Also,DB will temporarily increment if an address is indexed beyond the limits of the bank currently inDB.DB is ignored if a 24-bit address is specified as the operand to a data fetch/store instruction, or if the effective address is on direct (zero) page or thehardware stack. In the latter case, an implied bank$00 is used to generate the effective address.[16]
A further addition to the register set is the 16-bit direct page register (DP), which sets the base address for what was formerly called thezero page, but now referred to asdirect page. Direct page addressing uses an 8-bit address, which results in faster access than when a 16- or 24-bit address is used. Also, some addressing modes that offer indirection are only possible on direct page. In the 65(c)02, the direct page is always the first 256 bytes of memory, hence “zero page”. In native mode, the 65c816 can relocate direct (zero) page anywhere in bank$00 (the first 64 KB of memory) by writing the 16-bit starting address intoDP. There is a one-cycle access penalty ifDP is not set to an exact page boundary, that is, if the value inDP is not$xx00, wherexx is the most-significant byte.[17]
The current mode of operation is stored in the emulation (e) bit. Having already added the newx andm bits to the previous set of six flags in the status register (SR), there were not enough bits left to hold the new mode bit. Instead, a unique solution was used in which the mode bit was left "invisible", unable to be directly accessed. TheXCE (eXchangeCarry withEmulation) instruction exchanges the value of the emulation bit with the carry (c) bit, bit 0 inSR. For instance, if one wants to enter native mode after the processor has started up, one would useCLC to clear the carry bit, and thenXCE to write it to the emulation bit.[18] Returning to 65c02 emulation mode usesSEC followed byXCE.[19]
Internally, the 65c816 is a fully 16-bit design. Them andx bits inSR determine how the user registers (accumulator and index) appear to the rest of the system. Upon reset, the 65c816 starts in 6502 emulation mode, in whichm andx are locked to1. Hence the registers are locked to eight-bit size. The most significant byte (MSB) of the accumulator (theB-accumulator) is not directly accessible but can be swapped with the least significant byte (LSB) of the accumulator (theA-accumulator) by using theXBA instruction. There is no corresponding operation for the index registers (X andY), whose MSBs are locked at$00.
Upon being switched to native mode, the MSB ofX andY will be zero, and theB-accumulator will be unchanged. If them bit inSR is cleared, theB-accumulator will be "ganged" to theA-accumulator to form a 16-bit register (called theC-accumulator). A load/store or arithmetic/logical operation involving the accumulator or memory will be a 16-bit operation—two bus cycles are required to fetch/store a 16-bit value.
If thex bit inSR is cleared, both index registers will be set to 16 bits. If used to index an address, e.g.,LDA SOMEWHERE,X, the 16-bit value in the index register will be added to the base address to form the effective address.
If them bit inSR is set, the accumulator will return to being an 8-bit register and subsequent operations on the accumulator, with a few exceptions, will be 8-bit operations. TheB-accumulator will retain the value it had when the accumulator was set to 16 bits. The exceptions are the instructions that transfer the direct page register (DP) and stack pointer (SP) to/from the accumulator. These operations are always 16 bits wide in native mode, regardless of the condition of them bit inSR.
If thex bit inSR is set, not only will the index registers return to being 8 bits, whatever was in the MSB while they were 16 bits wide will be lost, something an assembly language programmer cannot afford to forget.[20]
Systems based on 65c816 variants:
