Synchronous Positive edge T Flip-Flop with Reset and Clock enable

libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;entityt_triggerisport(T,Reset,CLK,CLK_enable:instd_logic;Q:outstd_logic);endt_trigger;architecturebeh_t_triggeroft_triggerisbeginprocess(Reset,CLK)variabletemp:std_logic;beginif(rising_edge(CLK))then--sometimes you need to include a package for rising_edge, you can use CLK'EVENT AND CLK = '1' insteadifReset='1'thentemp:='0';elsifCLK_enable='1'thentemp:=Txortemp;endif;endif;Q<=temp;endprocess;endbeh_t_trigger;

Simulation Results

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