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VHDL for FPGA Design/4-Bit BCD Counter with Clock Enable

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<VHDL for FPGA Design
VHDL for FPGA Design

4-Bit BCD Up Counter with Clock Enable

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libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityCounter2_VHDLisport(Clock_enable_B:instd_logic;Clock:instd_logic;Reset:instd_logic;Output:outstd_logic_vector(0to3));endCounter2_VHDL;architectureBehavioralofCounter2_VHDLissignaltemp:std_logic_vector(0to3);beginprocess(Clock,Reset)beginifReset='1'thentemp<="0000";elsif(rising_edge(Clock))thenifClock_enable_B='0'theniftemp="1001"thentemp<="0000";elsetemp<=temp+1;endif;endif;endif;endprocess;Output<=temp;endBehavioral;

Simulation Results

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