| Type | Digital video connector | ||
|---|---|---|---|
| Production history | |||
| Designed | 2006 (Abandoned 2007) | ||
| Produced | None | ||
| Superseded | HDMI | ||
| Superseded by | DisplayPort | ||
| General specifications | |||
| Length | 10.7 mm (0.42 in) | ||
| Width | 17.3 mm (0.68 in) | ||
| Height | 3.7 mm (0.15 in) | ||
| Hot pluggable | Yes | ||
| External | Yes | ||
| Audio signal | No | ||
| Video signal | Yes | ||
| Pins |
| ||
| Electrical | |||
| Max. voltage | +5V | ||
| Max. current | 0.5 A | ||
| Data | |||
| Data signal | R,G,B data + clock and display data channel (TMDS) | ||
| Width | 36 bit (maximum) | ||
| Bitrate | 16 Gbit/s | ||
| Pinout | |||
 | |||
| External UDI receptacles for the (R)eceiver [display] and (T)ransmitter [computer] | |||
| Pin 1 | Reserved connector pin. No cable connection | (NC) | |
| Pin 2 | Reserved connector pin. No cable connection | (NC) | |
| Pin 3 | Reserved connector pin. No cable connection | (NC) | |
| Pin 4 | Shield for UDI_Data2[+/-] | GND | |
| Pin 5 | Positive side of UDI lane 2 data | UDI_Data2+ | |
| Pin 6 | Negative side of UDI lane 2 data | UDI_Data2- | |
| Pin 7 | Shield for UDI_Data1[+/-] | GND | |
| Pin 8 | Positive side of UDI lane 1 data | UDI_Data1+ | |
| Pin 9 | Negative side of UDI lane 1 data | UDI_Data1- | |
| Pin 10 | Shield for UDI_Data0[+/-] | GND | |
| Pin 11 | Positive side of UDI lane 0 data | UDI_Data0+ | |
| Pin 12 | Negative side of UDI lane 0 data | UDI_Data0- | |
| Pin 13 | Shield for UDI_Clk[+/-] | GND | |
| Pin 14 | Positive side of UDI differential reference clock | UDI_Clk+ | |
| Pin 15 | Negative side of UDI differential reference clock | UDI_Clk- | |
| Pin 16 | Discrete ground wire | GND | |
| Pin 17 | Consumer Electronics Control (optional) | CEC | |
| Pin 18 | UDI auxiliary power | UDI_APwr | |
| Pin 19 | UDI control clock | UDI_CtrlClk | |
| Pin 20 | UDI control data | UDI_CtrlData | |
| Pin 21 | Supply voltage for control link signals | UDI_EPwr | |
| Pin 22 | UDI link hot-plug detect | UDI_HPD | |
Unified Display Interface (UDI) was adigital videointerface specification released in 2006 which was based onDigital Visual Interface (DVI). It was intended to be a lower cost implementation while providing compatibility with existingHigh-Definition Multimedia Interface (HDMI) and DVI displays. Unlike HDMI, which is aimed athigh-definitionmultimediaconsumer electronics devices such as television monitors and DVD players, UDI was specifically targeted towards computer monitor and video card manufacturers and did not support the transfer of audio data. A contemporary rival standard,DisplayPort, gained significant industry support starting in 2007 and the UDI specification was abandoned shortly thereafter without having released any products.
On December 20, 2005, the UDI Special Interest Group (UDI SIG) was announced, along with a tentative specification called version 0.8.[1][2] The group, which worked on refining the specification and promoting the interface, was led byIntel[3] and includedApple Computer,Intel,LG,NVIDIA,Samsung, andSilicon Image Inc.[4]
The announcement of UDI lagged theDisplayPort standard by a few months, which had been unveiled by theVideo Electronics Standards Association (VESA) in May 2005. DisplayPort was being developed by a rival consortium includingATI Technologies, Samsung, NVIDIA,Dell,Hewlett-Packard, andMolex.[5] Fundamentally, DisplayPort transmits video in packets of data, while the preceding DVI and HDMI standards transmit raw video as a digital signal; UDI took an approach closer to DVI/HDMI.[6] The UDI specification 1.0 was finalized and released in July 2006. The differences between UDI andHDMI were kept to a minimum since both specifications were designed for long-term compatibility.[7] Again, UDI lagged DisplayPort by a few months, which had released its finalized version 1.0 specification in May 2006.[8]
The group changed its title in late 2006 from "special interest group" to "working group"[9] and contemporary press coverage noted that "UDI is weak when it comes to industry support", accurately predicting the future DisplayPort/HDMI duopoly.[10] In early 2007 Intel started supporting the rival DisplayPort standard; anonymous sources stated the licensing fees associated with HDMI and incorporation of HDCP into DisplayPort swayed Intel's support.[6][11] Other vendors started to use HDMI version 1.3,[12] and both Intel and Samsung withdrew their support from UDI. There have been no announcements made about UDI since early 2007 and the UDI website became no longer operational after 2007,[9] and it appears the UDI standard was abandoned before products were released.
There were two UDI implementations: "external profile" (for desktop computers and displays) and "embedded profile" (for the internal display of a laptop computer).[13]: §1.9
Under the external profile, data was transmitted using three differential data pairs and one differential clock pair using the TMDS encoding scheme.[13]: §1.9.1 The external profile is considered an extension of HDMI and is backwards-compatible with HDMI Rev. 1.2 displays; however, UDI does not carry audio information as it is targeted towards high-resolution computer monitors instead.[13]: §1.10.1 As HDMI is itself an extension of DVI with HDCP, UDI external profile is compatible with these standards as well.[13]: §1.10.2, 1.10.3
The embedded profile was slightly different, using either one or three differential pairs, each of which carried both data and clock information. The embedded profile uses an ANSI8b/10b encoding scheme instead.[13]: §1.9.2, 3.3.1, 3.3.2
UDI provided higher bandwidth than its predecessors (up to 16 Gbit/s in its first version, compared to 4.95 Gbit/s for HDMI 1.0)[11] and incorporated a form ofdigital rights management known asHDCP.[12]
The external and embedded connector implementations were electrically compatible and physically similar, each with a single row of contacts, but they had different form factors and contact counts. The "embedded" implementation was only specified for the display panel interface and had a single row of 26 contacts, while the "external" implementation had a single row of 22 contacts inside a metal shield with a physically keyed rectangular cross-section, resembling theUSB Type A connectors.[13]: §7.2.2, 7.3.2 The contacts were spaced on a pitch of 0.6 mm (0.024 in) (external)[13]: §7.2.2 and 1.0 mm (0.039 in) (embedded).[13]: §7.3.2
Three of the contacts were reserved for future upgrade possibilities.[13]: §7.2.1, 7.3.1 Transmit and receive plugs and receptacles were different physically, similar to peripheral cables with USB-A and USB-B on each end, requiring the UDI cable to be plugged in one way only.[13]: §7.2.2, 7.3.2 Bidirectional communication worked at a much lower data rate than that available for the single direction video datastream.
| Pin | Signal | Description |
|---|---|---|
| 1 | RSVD | Reserved; second mate |
| 2 | RSVD | Reserved; second mate |
| 3 | RSVD | Reserved; second mate |
| 4 | Gnd | UDI Data2 shield; second mate |
| 5 | UDI Data2+ | UDI differential data pair 2: +; second mate |
| 6 | UDI Data2- | UDI differential data pair 2: -; second mate |
| 7 | Gnd | UDI Data1 shield; second mate |
| 8 | UDI Data1+ | UDI differential data pair 1: +; second mate |
| 9 | UDI Data1- | UDI differential data pair 1: -; second mate |
| 10 | Gnd | UDI Data0 shield; second mate |
| 11 | UDI Data0+ | UDI differential data pair 0: +; second mate |
| 12 | UDI Data0- | UDI differential data pair 0: -; second mate |
| 13 | Gnd | UDI Clk shield; second mate |
| 14 | UDI Clk+ | UDI differential reference clock: +; second mate |
| 15 | UDI Clk- | UDI differential reference clock: -; second mate |
| 16 | Gnd | Ground; discrete wire; second mate |
| 17 | CEC[a] | Consumer Electronics Control (optional); second mate |
| 18 | UDI APwr[b] | UDI auxiliary power; second mate |
| 19 | UDI CtrlClk | UDI control clock; second mate |
| 20 | UDI CtrlData | UDI control data; second mate |
| 21 | UDI EPwr[a] | UDI power: +5V; third mate |
| 22 | UDI HPD | UDI hot-plug detect; third mate |
| — | Connector shell | first mate |
| Pin | Signal | Description |
|---|---|---|
| 1 | VDD UDL | Supply voltage for data link circuitry |
| 2 | VDD UDL | |
| 3 | VDD UDL | |
| 4 | VDD UDL | |
| 5 | VSS | Supply return for control and data link power |
| 6 | VSS | |
| 7 | VSS | |
| 8 | VSS | |
| 9 | UDI Data0+ | UDI lane 0 data; only used for ×3 lane width |
| 10 | UDI Data0+ | |
| 11 | GND | Shield for UDI Data0 |
| 12 | UDI Data1+ | UDI lane 1 data; used for ×1 and ×3 lane widths |
| 13 | UDI Data1- | |
| 14 | GND | Shield for UDI Data1 |
| 15 | UDI Data2+ | UDI lane 2 data; only used for ×3 lane width |
| 16 | UDI Data2- | |
| 17 | GND | Shield for UDI Data2 |
| 18 | RSVD | Reserved |
| 19 | RSVD | |
| 20 | RSVD | |
| 21 | (Test pin) | |
| 22 | GND | Ground return |
| 23 | UDI EPwr | Supply voltage for control link signals |
| 24 | UDI CtrlClk | UDI control link clock |
| 25 | UDI CtrlData | UDI control link data |
| 26 | UDI HPD | UDI link hot-plug detect |
What we have then is a re-run of the old USB vs Firewire debate: two standards [DisplayPort and HDMI] that do, give or take a plus point or two, the same job largely as well as each other. In each case, sufficiently large industry camps have formed around each to ensure neither will vanish, and vested intellectual property and licensing interests means there's little chance of the two coming together into a single standard.