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Why would it?Kurt Weber 7 July 2005 03:41 (UTC)

I did some heavy editing and added a lot of references. I think it's needed at this point when tere are very little publicly available documents from IBM. --Henriok

Many news sources are usingPower6 as the capitalization.

Fixed! Good call! --Henriok20:50, 21 May 2007 (UTC)Reply

This quote :"Dr Frank Soltis, an IBM chief scientist said IBM had solved power leakage problems associated with high frequency by using a combination of 90nm and 65nm parts in the POWER6 design"

not only needs a citation, but it is factually wrong. It should be removed

I'm sure it is, but not according to the article:IT Week, 08 Feb 2006. --Henriok12:28, 21 June 2007 (UTC)Reply

That is one article, from over a year ago, if you wish to keep it it'd be nice to have some proof that is more recent and authoritative.

I'll point out that Dr. Brad McCredie is the Chief Engineer on Power6, not Dr. Soltis.

Here are some other links:http://speleotrove.com/decimal/IBM-Power-Roadmap-McCredie.pdfhttp://www.mdronline.com/mpr/mpr_public/203501.htmlhttp://www-03.ibm.com/developerworks/blogs/page/powerarchitecture?entry=archaeology_101_digging_into_thehttp://www.iee.org/oncomms/sector/electronics/SectionNews/Object/AEEA16EF-DC2E-DFB1-F37FE2414CD9E6EF

- Anonymous IBMer32.97.110.14205:51, 23 June 2007 (UTC)Reply

The IT Week article also states that it has a 2 stage pipeline; Ars Technica gives a more plausible 15.

I don't think that the POWER6 is packaged on a MCM with eight dies like the POWER5, as the article states. My factsheet from IBM has no mention of this. Also, if one looked at the IBM press kit, the chips in one of the pictures shows one die per a chip. Can anyone confirm wether it is packaged in a MCM or not? --Rilak18:42, 18 August 2007 (UTC)Reply

The POWER5 comes in three different kinds of MCMs: dual-, quad- and octa-chip (one cache chip per CPU chip). The POWER6 comes in mono-chip packaging for now but IBM is planning for four-chip MCMs (eight cores) accordning to theReal World Tech article. Every configuration are not available from day one. For now it's just a singe chip module, but there seems to be at least four-CPU modules planned. The pictures of the packaging only reveals one chip. I don't know if the external L3 chip is located on another module or hidden inside the packaging. --Henriok12:28, 19 August 2007 (UTC)Reply

Just out of curiousity, what is the basic word length of this thing?Cardamon (talk)10:23, 27 November 2009 (UTC)Reply

POWER6 uses 64-bit registers but the Power ISA defines word length as 32 bits. --Henriok (talk)13:30, 27 November 2009 (UTC)Reply

The article states that it can do "two independent 32-bit reads or one 64-bit write per cycle". But the source (Information week) says nothing about the number of bits. I seriously doubt that the Power6 needs both read-ports of its D-Cache to fill a 64 bit register via two 32 bit loads.--85.216.120.20 (talk)13:01, 31 December 2009 (UTC)Reply