SSE3,Streaming SIMD Extensions 3, also known by itsIntel code namePrescott New Instructions (PNI),[1] is the third iteration of theSSE instruction set for theIA-32 (x86) architecture. Intel introduced SSE3 in 2004 with thePrescott revision of theirPentium 4 andCeleron D CPUs.[1] In April 2005,AMD introduced a subset of SSE3 in revision E (Venice and San Diego) of theirAthlon 64 CPUs.[2] The earlierSIMD instruction sets on thex86 platform, from oldest to newest, areMMX,3DNow! (developed by AMD, no longer supported on newer CPUs),SSE, andSSE2.
SSE3 contains 13 new instructions overSSE2.[3]
The most notable change is the capability to work horizontally in a register, as opposed to the more or less strictly vertical operation of all previous SSE instructions. More specifically, instructions to add and subtract the multiple values stored within a single register have been added.[4] These instructions can be used to speed up the implementation of a number ofDSP and3D operations. There is also a new instruction to convert floating point values to integers without having to change the global rounding mode, thus avoiding costlypipeline stalls. Finally, the extension addsLDDQU, an alternative misaligned integer vector load that has better performance onNetBurst based platforms for loads that cross cacheline boundaries.[5]
ADDSUBPDADDSUBPSHADDPDHADDPSHSUBPDHSUBPSLDDQUMOVDDUP,MOVSHDUP,MOVSLDUP[4]FISTTPFISTP instruction, but ignores the floating point control register's rounding mode settings and uses the "chop" (truncate) mode instead.[4] Allows omission of the expensive loading and re-loading of the control register in languages such as C where float-to-int conversion requires truncate behaviour by standard.MONITOR,MWAITMONITOR instruction is used to specify a memory address for monitoring, while theMWAIT instruction puts the processor into a low-power state and waits for a write event to the monitored address.[4]