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ThePowerPC e500 is a32-bitmicroprocessorcore fromFreescale Semiconductor. The core is compatible with the older PowerPC Book E specification as well as thePower ISA v.2.03.^{[citation needed]} It has a dual issue, seven-stagepipeline withFPUs (from version 2 onwards), 32/32 KiB data and instruction L1caches and 256, 512 or 1024 KiB L2 frontside cache. Speeds range from 533 MHz up to 1.5 GHz, and the core is designed to be highly configurable and meet the specific needs ofembedded applications with features likemulti-core operation interface for auxiliary application processing units (APU).

e500 powers the high-performancePowerQUICC IIIsystem on a chip (SoC)network processors and they all share a common naming scheme,MPC85xx. Freescale's newQorIQ is the evolutionary step from PowerQUICC III and will also be based on e500 cores.

There are three versions of the e500 core, namely the originale500v1, thee500v2 and thee500mc.

A 64-bit evolution of the e500mc core is called thee5500 core and was introduced in 2010, and a subsequente6500 core addedmultithreading capabilities in 2012.

• Support for the SPE (Signal Processing Engine) extensions. The integer register file is extended to a width of 64-bits. The non-SPE instructions only access and write to the low 32-bits. However the SIMD SPE instructions read and write from the full 64-bits. These extensions overlap with the string andAltiVec instructions.
• Support for SPESFP (Single Precision Embedded Scalar Floating Point). This is a new floating point unit that is distinct from the classic FPU, the latter of which is lacking in e500v1 and e500v2. SPESFP uses the integer register file. It is not completely IEEE754 compliant.

Key improvements in the e500v2 over the e500v1 include:

• Increase from 32-bit (4 GiB) to 36-bit (64 GiB) physical address space. This change means that e500v2-based devices often use a more advancedboard support package (BSP) than e500v1-based devices, as various peripheral units have moved to physical addresses higher than 4 GiB.
• Addition of 1 GiB and 4 GiB variable-page sizes
• Addition of DPESFP (double-precision embedded scalar floating point) support. Building on top of SPESFP, these instructions access both halves of the 64-bit integer register.
• Doubling in size and associativity of the MMU's second-level 4K-page array (from 256-entry 2-way to 512-entry 4-way)
• Increase from 3 to 5 maximum outstanding data cache misses
• Addition of the Alternate Time Base for cycle-granularity timestamps

Freescale introduced thee500mc in theQorIQ family of chips in June 2008. The e500mc has the following features:

• Power ISA v.2.06, which includeshypervisor andvirtualization functionality for embedded platforms.
• The "classic" floating-point unit has been reinstated.
• SPE, SPESFP, and DPESFP are all removed, and the integer register file is back to 32 bits.
• Support anything from two to more than 32 cores (not necessarily the same type of cores) on a single chip.
• Supports theCoreNet communications fabric for connecting cores and datapath accelerators.
• e500mc cores have private L2 caches but typically share other facilities like L3 caches, memory controllers, application specific acceleration cores, I/O and such.

AllPowerQUICC 85xx devices are based on e500v1 or e500v2 cores, most of them on the latter.

In June 2008 Freescale announced theQorIQ brand, microprocessors based on the e500 family of cores.

Infree and open source software, the e500/MPC85xx family (minus the e500mc, which has no SPE) is generally known as "PPC SPE" (powerpcspe), with the EABI known as "eabispe". BothGCC (before version 9) andLLVM^[1] offer support for compiling to this platform, andQEMU provides emulation.Debian used to offer an unofficial port for the e500v2 called powerpcspe.^[2]

• PowerQUICC
• QorIQ
• PowerPC e200
• PowerPC e5500

• Freescale's PowerQUICC page
• Freescale's PowerPC e500 Core Family Reference Manual

• PowerPC microprocessors
• Freescale microprocessors
• Power microprocessors

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