Theplanar process is amanufacturing process used in thesemiconductor industry to build individual components of atransistor, and in turn, connect those transistors together. It is the primary process by whichsiliconintegrated circuit chips are built, and it is the most commonly used method of producingjunctions during the manufacture ofsemiconductor devices.[1] The process utilizes thesurface passivation andthermal oxidation methods.
The planar process was developed atFairchild Semiconductor in 1959 and process proved to be one of the most important single advances in semiconductor technology.[1]
The key concept is to view a circuit in its two-dimensional projection (a plane), thus allowing the use ofphotographic processing concepts such as film negatives to mask the projection of light exposed chemicals. This allows the use of a series of exposures on a substrate (silicon) to createsilicon oxide (insulators) or doped regions (conductors). Together with the use of metallization, and the concepts ofp–n junction isolation andsurface passivation, it is possible to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.
The process involves the basic procedures ofsilicon dioxide (SiO2) oxidation, SiO2 etching and heat diffusion. The final steps involvesoxidizing the entire wafer with an SiO2 layer, etching contact vias to the transistors, and depositing a covering metal layer over theoxide, thus connecting the transistors without manually wiring them together.
In 1955 atBell Labs,Carl Frosch and Lincoln Derick accidentally grew a layer of silicon dioxide over a silicon wafer, for which they observedsurface passivation properties.[2][3] In 1957, Frosch and Derick were able to manufacture the first silicon dioxide field effect transistors, the first transistors in which drain and source were adjacent at the surface, showing that silicon dioxide surface passivation protected and insulated silicon wafers.[4]
At Bell Labs, the importance of Frosch's technique was immediately realized. Results of theirs circulated around Bell Labs in the form of BTL memos before being published in 1957. AtShockley Semiconductor, Shockley had circulated the preprint of their article in December 1956 to all his senior staff, includingJean Hoerni.[5][6][7][8] Later, Hoerni attended a meeting whereAtalla presented a paper about passivation based on the previous results at Bell Labs.[8] Taking advantage of silicon dioxide's passivating effect on the silicon surface, Hoerni proposed to make transistors that were protected by a layer of silicon dioxide.[8]
Jean Hoerni, while atFairchild Semiconductor, first patented the planar process in 1959.[9][10] K. E. Daburlos and H. J. Patterson of Bell Laboratories continued on the efforts of C. Frosch and L. Derick, and developed a process similar to Hoerni’s about the same time.[8] Together with the use of metallization (to join together the integrated circuits), and the concept ofp–n junction isolation (fromKurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from amonocrystalline siliconboule.
In 1959,Robert Noyce built on Hoerni's work with his conception of anintegrated circuit (IC), which added a layer of metal to the top of Hoerni's basic structure to connect different components, such as transistors,capacitors, orresistors, located on the same piece of silicon. The planar process provided a powerful way of implementing an integrated circuit that was superior to earlier conceptions of the integrated circuit.[11] Noyce's invention was the first monolithic IC chip.[12][13]
Early versions of the planar process used aphotolithography process using near-ultraviolet light from a mercury vapor lamp.As of 2011, small features are typically made with 193 nm "deep" UV lithography.[14] As of 2022, theASML NXE platform uses 13.5 nm extreme ultraviolet (EUV) light, generated by a tin-based plasma source, as part of theextreme ultraviolet lithography process.