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| General information | |
|---|---|
| Launched | 1990 |
| Designed by | IBM |
| Architecture and classification | |
| Instruction set | POWER ISA |
| History | |
| Successor | POWER2 |
| POWER,PowerPC, andPower ISA architectures |
|---|
| NXP (formerly Freescale and Motorola) |
| IBM |
|
| IBM/Nintendo |
| Other |
| Related links |
| Cancelled in gray,historic in italic |
ThePOWER1 is amulti-chipCPU developed andfabricated byIBM that implemented thePOWERinstruction set architecture (ISA). It was originally known as theRISC System/6000 CPU or, when in an abbreviated form, theRS/6000 CPU, before introduction of successors required the original name to be replaced with one that used the same naming scheme (POWERn) as its successors in order to differentiate it from the newer designs.
The POWER1 was introduced in 1990, with the introduction of the IBMRS/6000 POWERserverservers and POWERstationworkstations, which featured the POWER1 clocked at 20, 25 or 30MHz. The POWER1 received two upgrades, one in 1991, with the introduction of the POWER1+ and in 1992, with the introduction of POWER1++. These upgraded versions were clocked higher than the original POWER1, made possible by improvedsemiconductor processes. The POWER1+ was clocked slightly higher than the original POWER1, at frequencies of 25, 33 and 41 MHz, while the POWER1++ took the microarchitecture to its highest frequencies — 25, 33, 41.6, 45, 50 and 62.5 MHz. In September 1993, the POWER1 and its variants was succeeded by thePOWER2 (known briefly as the "RIOS2"), an evolution of the POWER1 microarchitecture.
The direct derivatives of the POWER1 are theRISC Single Chip (RSC), feature-reduced single-chip variant for entry-level RS/6000 systems, and theRAD6000, a radiation-hardened variant of the RSC for space applications. An indirect derivative of the POWER1 is thePowerPC 601, a feature-reduced variant of the RSC intended for consumer applications.
The POWER1 is notable as it represented a number of firsts for IBM and computing in general. It was IBM's firstRISC processor intended for high-end applications (theROMP was considered a commercial failure and was not used in high-end workstations), it was the first to implement the then new POWER instruction set architecture and it was IBM's first successful RISC processor. For computing firsts, the POWER1 would be known for being the first CPU to implement some form ofregister renaming andout-of-order execution, a technique that improves the performance ofsuperscalar processors but was previously reserved formainframes.
The POWER1 was also the origin for the highly successful families ofPOWER,PowerPC andPower ISA processors that followed it, measuring in hundreds of different implementations.
The open sourceGCC compiler removed support for POWER1 (RIOS) and POWER2 (RIOS2) in the 4.5 release.[1]
The POWER1 is a32-bit two-way superscalar CPU. It contains three major execution units, afixed-point unit (FXU), abranch unit (BPU) and afloating point unit (FPU). Although the POWER1 is a 32-bit CPU with a 32-bitphysical address, itsvirtual address is 52 bits long. The larger virtual address space was chosen because it was beneficial for the performance of applications, allowing each one to have a large 4GB address range.
The POWER1 is abig-endian CPU that uses aHarvard stylecache hierarchy with separate instruction and data caches. The instruction cache, referred to as the "I-cache" by IBM, is 8 KB in size and istwo-way set associative with a line size of 64 bytes. The I-cache is located on the ICU chip. The data cache, referred to as the "D-cache" by IBM, is 32 KB in size for RIOS.9 configurations and 64 KB in size for RIOS-1 configurations. The D-cache is four-way set associative with a line size of 128 bytes. The D-cache employs a store-back scheme, where data that is to be stored is written to the cache instead of the memory in order to reduce the number of writes destined for the memory. The store-back scheme is used to prevent the CPU from monopolizing access to the memory.
Although the POWER1 was a high-end design, it was not capable ofmultiprocessing, and as such was disadvantaged, as the only way performance could be improved was byclocking the CPU higher, which was difficult to do with such a large multi-chip design. IBM used clustering to overcome this disadvantage in POWER1 systems, allowing them to effectively function as if they were multiprocessing systems, a concept proven by the popularity ofIBM RS/6000 SP based on the POWER1. As the POWER1 was the basis of the POWER2 andP2SC microprocessors, the lack of multiprocessing was passed on to these later POWER processors. Multiprocessing was not supported until the introduction of thePOWER3 in 1998.
The POWER1 is a multi-chip CPU built from separate chips that are connected to each other by buses. The POWER1 consists of aninstruction-cache unit (ICU), afixed-point unit (FXU), afloating point unit (FPU), a number ofdata-cache units (DCU), astorage-control unit (SCU) and anI/O unit. Due to its modular design, IBM was able to create two configurations by simply varying the number of DCUs,RIOS-1 and aRIOS.9. The RIOS-1 configuration has four DCUs, the intended amount, and was clocked at up to 40 MHz, whereas the RIOS.9 CPU had two DCUs and was clocked at lower frequencies.
The chips are mounted on the “CPU planar”, aprinted circuit board (PCB), using through-hole technology. Due to the large number of chips with widebuses, the PCB has eight planes for routing wires, four for power and ground and four for signals. There are two signal planes on each side of the board, while the four power and ground planes are in the center.
The chips that make up the POWER1 are fabricated in a 1.0 μmCMOS process with three layers of interconnect. The chips are packaged inceramic pin grid array (CPGA) packages that can have up to 300 pins and dissipate a maximum of 4W of heat each. The total number oftransistors featured by the POWER1, assuming that it is a RIOS-1 configuration, is 6.9 million, with 2.04 million used for logic and 4.86 million used for memory. The die area of all the chips combined is 1,284 mm2. The total number of signal pins is 1,464.
The ICU contains the instruction cache, referred to as the "I-cache" by IBM and thebranch processing unit (BPU). The BPU contains theprogram counter, the condition code register and a loop register. The ICU contains 0.75 million transistors with 0.2 million used for logic and 0.55 million used forSRAM. The ICUdie measures approximately 160 mm2 (12.7 × 12.7 mm).
The BPU was capable of dispatching multiple instructions to the fixed and floating point instructions queues while it was executing a program flow control instruction (up to four simultaneously and out of order). Speculativebranches were also supported by using a prediction bit in the branch instructions, with the results discarded before being saved if the branch was not taken. The alternate instruction would be buffered and discarded if the branch was taken. Consequently,subroutine calls andinterrupts are dealt with without incurring branch penalties.
The condition code register has eight field sets, with the first two reserved for fixed and floating point instructions and the seventh forvector instructions. The rest of the fields could be used by other instructions. The loop register is a counter for "decrement and branch on zero" loops with no branch penalty, a feature similar to those found in someDSPs such as the TMS320C30.
The FXU is responsible for decoding and executing all fixed-point instructions and floating-point load and store instructions. For execution, the FXU contains the POWER1's fixed-point register file, an arithmetic logic unit (ALU) for general instructions, and a dedicated fixed-point multiply and divide unit. It also contains instruction buffers that receive both fixed- and floating-point instructions from the ICU, passing on the floating-point instructions to the FPU, and a 128-entry two-way set-associative D-TLB for address translation. The FXU contains approximately 0.5 million transistors, with 0.25 million used for logic and 0.25 used for memory, on a die measuring approximately 160 mm2.
The POWER1's floating point unit executes floating-point instructions issue by the ICU. The FPU ispipelined and can executesingle precision (32-bit) anddouble precision (64-bit) instructions. It is capable of performingmultiply-add instructions, which contributed to the POWER1's high floating point performance. In most processors, a multiply and an add, which is common in technical and scientific floating-point code, cannot be executed in one cycle, as in the POWER1. Use offused multiply–add also means that the data is only rounded once, improving the precision of the result slightly.
The floating-point register file is also located on the FPU chip. It contains 32 64-bit floating-point registers, six rename registers and two registers that are used by divide instructions.
The POWER1 has a 64 KBdata cache implemented through four identical data-cache units (DCU), each containing 16 KB of data cache. The cache and the buses that connect the DCU to the other chips are ECC protected. The DCUs also provide the interface to the memory. If two DCUs are present (RIOS.9 configuration), the memory bus is 64 bits wide, and if four DCUs are present (RIOS-1 configuration), the memory bus is 128 bits wide. The memory interface portion of the DCUs provide three features that improves the reliability and availability of the memory:memory scrubbing,ECC andbit steering. Each DCU contains approximately 1.125 million transistors, with 0.175 million used for logic and 0.95 million used for SRAM, on a die measuring approximately 130 mm² (11.3 × 11.3 mm).
The POWER1 is controlled by the SCU chip. All communications between the ICU, FXU and DCU chips as well as thememory andI/O devices is arbitrated by the SCU. Although the DCUs provide the means to perform memory scrubbing, it is the SCU that controls the process. The SCU contains approximately 0.23 million transistors, all of them for logic, on a die measuring approximately 130 mm2.
The POWER1's I/O interfaces are implemented by the I/O unit, which contains an I/O channel controller (IOCC) and twoserial link adapters (SLAs). The IOCC implements theMicro Channel interface and controls both I/O andDMA transactions between the Micro Channel adapters and the system memory. The two SLAs each implement a serialfibre optic link, which are intended to connect RS/6000 systems together. The optical links were not supported at the time of the RS/6000's release. The I/O unit contains approximately 0.5 million transistors, with 0.3 million used for logic and 0.2 million used for memory, on a die measuring approximately 160 mm2.