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Opteron

From Wikipedia, the free encyclopedia
Server and workstation processor line by AMD
Not to be confused withOperon.
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Opteron
General information
LaunchedApril 2003
DiscontinuedEarly 2017
Common manufacturer
  • AMD
Performance
Max.CPUclock rate1.4 GHz to 3.5 GHz
HyperTransport speeds800 MHz to 3200 MHz
Physical specifications
Cores
  • 1, 2, 4, 6, 8, 12, 16
Sockets
Architecture and classification
Technology node130 nm to 28 nm
Instruction setx86-64,ARMv8-A
History
PredecessorAthlon MP
SuccessorsEpyc (server),Ryzen Threadripper/Threadripper Pro (workstation)

Opteron is a discontinuedx86 server and workstationprocessor line fromAMD, and is the first processor that supports theAMD64instruction set architecture (known generically asx86-64). It was released on April 22, 2003, with theSledgeHammer core (K8) and was intended to compete in theserver andworkstation markets, particularly in the same segment as the IntelXeon processor. Processors based on theAMD K10 microarchitecture (codenamedBarcelona) were announced on September 10, 2007, featuring a newquad-core configuration. The last released Opteron CPUs are thePiledriver-based Opteron 4300 and 6300 series processors, codenamed "Seoul" and "Abu Dhabi" respectively.

In January 2016, the firstARMv8-A based Opteron-branded SoC was released,[1] though it is unclear what, if any, heritage this Opteron-branded product line shares with the original Opteron technology other than intended use in the server space.

Technical description

[edit]
Opteron 2212
Back of "Magny-Cours" processor (OS6132VAT8EGO)

Key capabilities

[edit]

Opteron combines two important capabilities in a single processor:

  1. native execution of legacy x8632-bit applications without speed penalties
  2. native execution of x86-6464-bit applications

The first capability is notable because at the time of Opteron's introduction, the only other64-bit architecture marketed with32-bitx86 compatibility (Intel'sItanium) ranx86 legacy-applications only with significant speed degradation. The second capability, by itself, is less noteworthy, as majorRISC architectures (such asSPARC,Alpha,PA-RISC,PowerPC,MIPS) have been 64-bit for many years. In combining these two capabilities, however, the Opteron earned recognition for its ability to run the vast installed base of x86 applications economically, while simultaneously offering an upgrade path to64-bit computing.

The Opteron processor possesses an integratedmemory controller supportingDDR SDRAM,DDR2 SDRAM orDDR3 SDRAM (depending on processor generation). This both reduces the latency penalty for accessing the mainRAM and eliminates the need for a separatenorthbridge chip.

Multi-processor features

[edit]

In multi-processor systems (more than one Opteron on a singlemotherboard), theCPUs communicate using theDirect Connect Architecture over high-speedHyperTransport links. Each CPU can access the main memory of another processor, transparent to the programmer. The Opteron approach to multi-processing is not the same as standardsymmetric multiprocessing; instead of having one bank of memory for all CPUs, each CPU has its own memory. Thus the Opteron is aNon-Uniform Memory Access (NUMA) architecture. The Opteron CPU directly supports up to an 8-way configuration, which can be found in mid-level servers. Enterprise-level servers use additional (and expensive) routing chips to support more than 8 CPUs per box.

In a variety of computing benchmarks, the Opteron architecture has demonstrated better multi-processor scaling than the IntelXeon[2] which did not have a point to point system until QPI and integrated memory controllers with the Nehalem design. This is primarily because adding another Opteron processor increases memory bandwidth, while that is not always the case for Xeon systems, and the fact that the Opterons use aswitched fabric, rather than a sharedbus. In particular, the Opteron's integrated memory controller allows the CPU to access localRAM very quickly. In contrast, multiprocessor Xeon system CPUs share only two common buses for both processor-processor and processor-memory communication. As the number of CPUs increases in a typical Xeon system,contention for the shared bus causes computing efficiency to drop. Intel migrated to a memory architecture similar to the Opteron's for theIntel Core i7 family of processors and their Xeon derivatives.

Multi-core Opterons

[edit]
Quad-core "Barcelona" Opteron
Six-core "Istanbul" Opteron

In April 2005, AMD introduced its first multi-core Opterons. At the time, AMD's use of the term multi-core in practice meantdual-core; each physical Opteron chip contained two processor cores. This effectively doubled the computing performance available to each motherboard processor socket. One socket could then deliver the performance of two processors, two sockets could deliver the performance of four processors, and so on. Because motherboard costs increase dramatically as the number of CPU sockets increase, multicore CPUs enable a multiprocessing system to be built at lower cost.

AMD's model number scheme has changed somewhat in light of its new multicore lineup. At the time of its introduction, AMD's fastest multicore Opteron was the model 875, with two cores running at 2.2GHz each. AMD's fastest single-core Opteron at this time was the model 252, with one core running at 2.6 GHz. Formultithreaded applications, or many single threaded applications, the model 875 would be much faster than the model 252.

Second-generation Opterons are offered in three series: the 1000 Series (single socket only), the 2000 Series (dual socket-capable), and the 8000 Series (quad or octo socket-capable). The 1000 Series uses theAM2 socket. The 2000 Series and 8000 Series useSocket F.[1]

AMD announced its third-generationquad-core Opteron chips on September 10, 2007[3][4] with hardware vendors announcing servers in the following month. Based on a core design codenamedBarcelona, new power and thermal management techniques were planned for the chips. Earlier dual core DDR2 based platforms were upgradeable to quad core chips.[5]The fourth generation was announced in June 2009 with theIstanbul hexa-cores. It introducedHT Assist, an additional directory for data location, reducing the overhead for probing and broadcasts. HT Assist uses 1 MB L3 cache per CPU when activated.[6]

In March 2010 AMD released theMagny-Cours Opteron 6100 series CPUs forSocket G34. These are 8- and 12-coremulti-chip module CPUs consisting of two four or six-core dies with aHyperTransport 3.1 link connecting the two dies. These CPUs updated the multi-socket Opteron platform to use DDR3 memory and increased the maximum HyperTransport link speed from 2.40 GHz (4.80 GT/s) for theIstanbul CPUs to 3.20 GHz (6.40 GT/s).

AMD changed the naming scheme for its Opteron models. Opteron 4000 series CPUs on Socket C32 (released July 2010) are dual-socket capable and are targeted at uniprocessor and dual-processor uses. The Opteron 6000 series CPUs on Socket G34 are quad-socket capable and are targeted at high-end dual-processor and quad-processor applications.

CPU socket models

[edit]

Socket 939

[edit]

AMD releasedSocket 939 Opterons, reducing the cost of motherboards for low-end servers and workstations. Except for the fact they have 1 MB L2 cache (versus 512 KB for the Athlon 64) the Socket 939 Opterons are identical to the San Diego and Toledo coreAthlon 64s, but are run at lower clock speeds than the cores are capable of, making them more stable.

Socket AM2

[edit]

Socket AM2 Opterons are available for servers that only have a single-chip setup. Codenamed Santa Ana, rev. F dual core AM2 Opterons feature 2 × 1 MB L2 cache, unlike the majority of theirAthlon 64 X2 cousins which feature 2 × 512 KB L2 cache. These CPUs are given model numbers ranging from 1210 to 1224.

Socket AM2+

[edit]

AMD introduced three quad-core Opterons on Socket AM2+ for single-CPU servers in 2007. These CPUs are produced on a 65 nm manufacturing process and are similar to theAgenaPhenom X4 CPUs. The Socket AM2+ quad-core Opterons are code-named "Budapest". The Socket AM2+ Opterons carry model numbers of 1352 (2.10 GHz), 1354 (2.20 GHz), and 1356 (2.30 GHz).

Socket AM3

[edit]

AMD introduced three quad-core Opterons on Socket AM3 for single-CPU servers in 2009. These CPUs are produced on a 45 nm manufacturing process and are similar to theDeneb-based Phenom II X4 CPUs. The Socket AM3 quad-core Opterons are code-named "Suzuka". These CPUs carry model numbers of 1381 (2.50 GHz), 1385 (2.70 GHz), and 1389 (2.90 GHz).

Socket AM3+

[edit]

Socket AM3+ was introduced in 2011 and is a modification of AM3 for theBulldozer microarchitecture. Opteron CPUs in the AM3+ package are named Opteron 3xxx.

Socket F

[edit]

Socket F (LGA 1207 contacts) is AMD’s second generation of Opteron socket. This socket supports processors such as the Santa Rosa, Barcelona, Shanghai, and Istanbul codenamed processors. the "liddedland grid array" socket adds support forDDR2 SDRAM and improvedHyperTransport version 3 connectivity. Physically the socket and processor package are nearly identical, although not generally compatible withsocket 1207 FX.

Socket G34

[edit]

Socket G34 (LGA 1944 contacts) is one of the third generation of Opteron sockets, along withSocket C32. This socket supportsMagny-Cours Opteron 6100, Bulldozer-basedInterlagos Opteron 6200, and Piledriver-based "Abu Dhabi" Opteron 6300 series processors. This socket supports four channels ofDDR3 SDRAM (two per CPU die). Unlike previous multi-CPU Opteron sockets, Socket G34 CPUs will function with unbuffered ECC or non-ECC RAM in addition to the traditional registered ECC RAM.

Socket C32

[edit]

Socket C32 (LGA 1207 contacts) is the other member of the third generation of Opteron sockets. This socket is physically similar toSocket F but is not compatible with Socket F CPUs. Socket C32 uses DDR3 SDRAM and is keyed differently so as to prevent the insertion of Socket F CPUs that can use only DDR2 SDRAM. Like Socket G34, Socket C32 CPUs will be able to use unbuffered ECC or non-ECC RAM in addition to registered ECC SDRAM.

Micro-architecture update
[edit]

The Opteron line saw an update with the implementation of theAMD K10 microarchitecture. New processors, launched in the third quarter of 2007 (codenameBarcelona), incorporate a variety of improvements, particularly in memory prefetching, speculative loads,SIMD execution andbranch prediction, yielding an appreciable performance improvement over K8-based Opterons, within the same power envelope.[7]

In 2007 AMD introduced a scheme to characterize the power consumption of new processors under "average" daily usage, namedaverage CPU power (ACP).

Socket FT3

[edit]

The Opteron X1150 and Opteron X2150 APU are used with the BGA-769 orSocket FT3.[8]

Features

[edit]

APUs

[edit]

SeeAPU features table

Models

[edit]

For Socket 940 and Socket 939 Opterons, each chip has a three-digit model number, in the formOpteronXYY. For Socket F and Socket AM2 Opterons, each chip has a four-digit model number, in the formOpteronXZYY. For all first, second, and third-generation Opterons, the first digit (theX) specifies the number of CPUs on the target machine:

For Socket F and Socket AM2 Opterons, the second digit (theZ) represents the processor generation. Presently, only2 (dual-core, DDR2),3 (quad-core, DDR2) and4 (six-core, DDR2) are used.

Socket C32 and G34 Opterons use a new four-digit numbering scheme. The first digit refers to the number of CPUs in the target machine:

  • 4 – Designed for uniprocessor and dual-processor systems.
  • 6 – Designed for dual-processor and four-processor systems.

Like the previous second and third generation Opterons, the second number refers to the processor generation. "1" refers to AMD K10-based units (Magny-Cours andLisbon), "2" refers to theBulldozer-basedInterlagos,Valencia, andZurich-based units, and "3" refers to thePiledriver-basedAbu Dhabi,Seoul, andDelhi-based units.

For all Opterons, the last two digits in the model number (theYY) indicate the clock frequency of a CPU, a higher number indicating a higher clock frequency. This speed indication is comparable to processors of the same generation if they have the same amount of cores, single-cores and dual-cores have different indications despite sometimes having the same clock frequency.

The suffixHE orEE indicates a high-efficiency/energy-efficiency model having a lowerTDP than a standard Opteron. The suffixSE indicates a top-of-the-line model having a higher TDP than a standard Opteron.

Starting from 65 nm fabrication process, the Opteron codenames have been based onFormula 1 hosting cities; AMD has a long term sponsorship with F1's most successful team,Ferrari.

AMD Opteron processor family
LogoServer
CodenameProcessDate releasedCores
AMD Opteron logo as of 2003SledgeHammer130 nmApr 20031
Venus90 nmDec 2004
TroyDec 2004
AthensDec 2004
DenmarkAug 20052
ItalyMay 2005
EgyptApr 2005
Santa AnaAug 2006
Santa RosaAug 2006
AMD Opteron logo as of 2008Barcelona65 nmSep 20074
BudapestApr 2008
Shanghai45 nmNov 2008
IstanbulJun 20096
LisbonJun 20104, 6
Magny-CoursMar 20108, 12
AMD Opteron logo as of 2011Valencia32 nmNov 20114, 6, 8
InterlagosNov 20114, 8, 12, 16
ZurichMar 20124, 8
Abu DhabiNov 20124, 8, 12, 16
DelhiDec 20124, 8
SeoulDec 20124, 6, 8
Kyoto28 nmMay 20132, 4
SeattleJan 20164, 8
TorontoJun 20172, 4
List of AMD Opteron microprocessors

Opteron (130 nm SOI)

[edit]

Single-core –SledgeHammer (1yy, 2yy, 8yy)

[edit]

Opteron (90 nm SOI, DDR)

[edit]

Single-core –Venus (1yy),Troy (2yy),Athens (8yy)

[edit]

Dual-core –Denmark (1yy),Italy (2yy),Egypt (8yy)

[edit]

Opteron (90 nm SOI, DDR2)

[edit]

Dual-core –Santa Ana (12yy),Santa Rosa (22yy, 82yy)

[edit]

Opteron (65 nm SOI)

[edit]

Quad-core –Barcelona (23xx, 83xx) 2360/8360 and below,Budapest (13yy) 1356 and below

[edit]

Opteron (45 nm SOI)

[edit]

Quad-core –Shanghai (23xx, 83xx) 2370/8370 and above,Suzuka (13yy) 1381 and above

[edit]
  • CPU steppings: C2
  • L3 cache: 6 MB, shared
  • Clock rate: 2.3–2.9 GHz
  • HyperTransport 1.0, 3.0
  • 20% reduction in idle power consumption[10]
  • support for DDR2 800 MHz memory (Socket F)[11]
  • support for DDR3 1333 MHz memory (Socket AM3)

6-core –Istanbul (24xx, 84xx)

[edit]

Released June 1, 2009.

  • CPU steppings: D0
  • L3 cache: 6 MB, shared
  • Clock rate: 2.2–2.8 GHz
  • HyperTransport 3.0
  • HT Assist
  • Support for DDR2 800 MHz memory[11]

8-core –Magny-Cours MCM (6124–6140)

[edit]

Released March 29, 2010.

  • CPU steppings: D1
  • Multi-chip module consisting of two quad-core dies
  • L2 cache: 8 × 512 KB
  • L3 cache: 2 × 6 MB, shared
  • Clockrate: 2.0–2.6 GHz
  • Four HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
  • HT Assist
  • Support for DDR3 1333 MHz memory
  • Socket G34

12-core –Magny-Cours MCM (6164-6180SE)

[edit]

Released March 29, 2010

  • CPU steppings: D1
  • Multi-chip module consisting of two hexa-core dies
  • L2 cache, 12 × 512 KB
  • L3 cache: 2 × 6 MB, shared
  • Clock rate: 1.7–2.5 GHz
  • Four HyperTransport 3.1 links at 3.2 GHz (6.40 GT/s)
  • HT Assist
  • Support for DDR3 1333 MHz memory
  • Socket G34

Quad-core –Lisbon (4122, 4130)

[edit]

Released June 23, 2010

  • CPU steppings: D0
  • L3 cache: 6 MB
  • Clock rate: 2.2 GHz (4122), 2.6 GHz (4130)
  • Two HyperTransport links at 3.2 GHz (6.40 GT/s)
  • HT Assist
  • Support for DDR3-1333 memory
  • Socket C32

Hex-core –Lisbon (4162–4184)

[edit]

Released June 23, 2010

  • CPU steppings: D1
  • L3 cache: 6 MB
  • Clock rate: 1.7–2.8 GHz
  • Two HyperTransport links at 3.2 GHz (6.40 GT/s)
  • HT Assist
  • Support for DDR3-1333 memory
  • Socket C32

Opteron (32 nm SOI) – First GenerationBulldozer Microarchitecture

[edit]
Main article:Bulldozer (microarchitecture)

Quad-core –Zurich (3250–3260)

[edit]

Released March 20, 2012.

  • CPU steppings: B2
  • Single processorBulldozer module
  • L2 cache: 2 × 2 MB
  • L3 cache: 4 MB
  • Clock rate: 2.5 GHz (3250) – 2.7 GHz (3260)
  • HyperTransport 3 (5.2 GT/s)
  • HT Assist
  • Support for DDR3 1866 MHz memory
  • Turbo CORE support, up to 3.5 GHz (3250), up to 3.7 GHz (3260)
  • Supports uniprocessor configurations only
  • Socket AM3+

Eight-core –Zurich (3280)

[edit]

Released March 20, 2012.

  • CPU steppings: B2
  • Single processorBulldozer module
  • L2 cache: 4 × 2 MB
  • L3 cache: 8 MB
  • Clock rate: 2.4 GHz
  • HyperTransport 3 (5.2 GT/s)
  • HT Assist
  • Support for DDR3 1866 MHz memory
  • Turbo CORE support, up to 3.5 GHz
  • Supports uniprocessor configurations only
  • Socket AM3+

6-core –Valencia (4226–4238)

[edit]

Released November 14, 2011.

  • CPU steppings: B2
  • Single die consisting of three dual-core Bulldozer modules
  • L2 cache: 6 MB
  • L3 cache: 8 MB, shared
  • Clock rate: 2.7–3.3 GHz (up to 3.1–3.7 GHz with Turbo CORE)
  • Two HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
  • HT Assist
  • Support for DDR3 1866 MHz memory
  • Turbo CORE support
  • Supports up to dual-processor configurations
  • Socket C32

8-core –Valencia (4256 HE-4284)

[edit]

Released November 14, 2011.

  • CPU steppings: B2
  • Single die consisting of four dual-core Bulldozer modules
  • L2 cache: 8 MB
  • L3 cache: 8 MB, shared
  • Clockrate: 1.6–3.0 GHz (up to 3.0-3.7 GHz with Turbo CORE)
  • Two HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
  • HT Assist
  • Support for DDR3 1866 MHz memory
  • Turbo CORE support
  • Supports up to dual-processor configurations
  • Socket C32

Quad-core –Interlagos MCM (6204)

[edit]

Released November 14, 2011.

  • CPU steppings: B2
  • Multi-chip module consisting of two dies, each with one dual-coreBulldozer module
  • L2 cache: 2 × 2 MB
  • L3 cache: 2 × 8 MB, shared
  • Clockrate: 3.3 GHz
  • HyperTransport 3 at 3.2 GHz (6.40 GT/s)
  • HT Assist
  • Support for DDR3 1866 MHz memory
  • Does not support Turbo CORE
  • Supports up to quad-processor configurations
  • Socket G34

8-core –Interlagos (6212, 6220)

[edit]

Released November 14, 2011.

  • CPU steppings: B2
  • Multi-chip module consisting of two dies, each with two dual-core Bulldozer modules
  • L2 cache: 2 × 4 MB
  • L3 cache: 2 × 8 MB, shared
  • Clockrate: 2.6, 3.0 GHz (up to 3.2 and 3.6 GHz with Turbo CORE)
  • Four HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
  • HT Assist
  • Support for DDR3 1866 MHz memory
  • Turbo CORE support
  • Supports up to quad-processor configurations
  • Socket G34

12-core –Interlagos (6234, 6238)

[edit]

Released November 14, 2011.

  • CPU steppings: B2
  • Multi-chip module consisting of two dies, each with three dual-core Bulldozer modules
  • L2 cache: 2 × 6 MB
  • L3 cache: 2 × 8 MB, shared
  • Clock rate: 2.4, 2.6 GHz (up to 3.1 and 3.3 GHz with Turbo CORE)
  • Four HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
  • HT Assist
  • Support for DDR3 1866 MHz memory
  • Turbo CORE support
  • Supports up to quad-processor configurations
  • Socket G34

16-core –Interlagos (6262 HE-6284 SE)

[edit]

Released November 14, 2011.

  • CPU steppings: B2
  • Multi-chip module consisting of two dies, each with four dual-core Bulldozer modules
  • L2 cache: 2 × 8 MB
  • L3 cache: 2 × 8 MB, shared
  • Clock rate: 1.6–2.7 GHz (up to 2.9-3.5 GHz with Turbo CORE)
  • Four HyperTransport 3.1 at 3.2 GHz (6.40 GT/s)
  • HT Assist
  • Support for DDR3 1866 MHz memory
  • Turbo CORE support
  • Supports up to quad-processor configurations
  • Socket G34

Opteron (32 nm SOI) –Piledriver microarchitecture

[edit]
Main article:Piledriver (microarchitecture)

Quad-core –Delhi (3320 EE, 3350 HE)

[edit]

Released December 4, 2012.

  • CPU steppings: C0
  • Single die consisting of twoPiledriver modules
  • L2 cache: 2 × 2 MB
  • L3 cache: 8 MB, shared
  • Clockrate: 1.9 GHz (3320 EE) – 2.8 GHz (3350 HE)
  • 1 × HyperTransport 3 (5.2 GT/s per link)
  • HT Assist
  • Support for DDR3 1866 MHz memory
  • Turbo CORE support, up to 2.5 GHz (3320 EE), up to 3.8 GHz (3350 HE)
  • Supports uniprocessor configurations only
  • Socket AM3+

Eight-core –Delhi (3380)

[edit]

Released December 4, 2012.

  • CPU steppings: C0
  • Single die consisting of fourPiledriver modules
  • L2 cache: 4 × 2 MB
  • L3 cache: 8 MB, shared
  • Clock rate: 2.6 GHz
  • 1 × HyperTransport 3 (5.2 GT/s per link)
  • HT Assist
  • Support for DDR3 1866 MHz memory
  • Turbo CORE support, pp to 3.6 GHz
  • Supports uniprocessor configurations only
  • Socket AM3+

4-core –Seoul (4310 EE)

[edit]

Released December 4, 2012

  • CPU steppings: C0
  • Single die consisting of twoPiledriver modules
  • L2 cache: 2 × 2 MB
  • L3 cache: 8 MB, shared
  • Clock rate: 2.2 GHz
  • 2 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
  • HT Assist
  • Support for DDR3 1866 MHz memory
  • Turbo CORE support, up to 3.0 GHz
  • Supports up to dual-processor configurations
  • Socket C32

6-core –Seoul (4332 HE – 4340)

[edit]

Released December 4, 2012

  • CPU steppings: C0
  • Single die consisting of threePiledriver modules
  • L2 cache: 3 × 2 MB
  • L3 cache: 8 MB, shared
  • Clockrate: 3.0 GHz (4332 HE) – 3.5 GHz (4340)
  • 2 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
  • HT Assist
  • Support for DDR3 1866 MHz memory
  • Turbo CORE support, from 3.5 GHz (4334) to 3.8 GHz (4340)
  • Supports up to dual-processor configurations
  • Socket C32

8-core –Seoul (4376 HE and above)

[edit]

Released December 4, 2012

  • CPU steppings: C0
  • Single die consisting of fourPiledriver modules
  • L2 cache: 4 × 2 MB
  • L3 cache: 8 MB, shared
  • Clock rate: 2.6 GHz (4376 HE) – 3.1 GHz (4386)
  • 2 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
  • HT Assist
  • Support for DDR3 1866 MHz memory
  • Turbo CORE support, from 3.6 GHz (4376 HE) to 3.8 GHz (4386)
  • Supports up to dual-processor configurations
  • Socket C32

Quad-core –Abu Dhabi MCM (6308)

[edit]

Released November 5, 2012.

  • CPU steppings: C0
  • Multi-chip module consisting of two dies, each with onePiledriver module
  • L2 cache: 2 MB per die (4 MB total)
  • L3 cache: 2 × 8 MB, shared within each die
  • Clock rate: 3.5 GHz
  • 4 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
  • HT Assist
  • Support for DDR3 1866 MHz memory
  • Does not support Turbo CORE
  • Supports up to quad-processor configurations
  • Socket G34

Eight-core –Abu Dhabi MCM (6320, 6328)

[edit]

Released November 5, 2012.

  • CPU steppings: C0
  • Multi-chip module consisting of two dies, each with twoPiledriver module
  • L2 cache: 2 × 2 MB per die (8 MB total)
  • L2 cache: 2 × 8 MB, shared within each die
  • Clock rate: 2.8 GHz (6320) – 3.2 GHz (6328)
  • 4 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
  • HT Assist
  • Support for DDR3 1866 MHz memory
  • Turbo CORE support, from 3.3 GHz (6320) to 3.8 GHz (6328)
  • Supports up to quad-processor configurations
  • Socket G34

12-core –Abu Dhabi MCM (6344, 6348)

[edit]

Released November 5, 2012.

  • CPU steppings: C0
  • Multi-chip module consisting of two dies, each with threePiledriver module
  • L2 cache: 3 × 2 MB per die (12 MB total)
  • L3 cache: 2 × 8 MB, shared within each die
  • Clock rate: 2.6 GHz (6344) – 2.8 GHz (6348)
  • 4 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
  • HT Assist
  • Support for DDR3 1866 MHz memory
  • Turbo CORE support, from 3.2 GHz (6344) to 3.4 GHz (6348)
  • Supports up to quad-processor configurations
  • Socket G34

16-core –Abu Dhabi MCM (6366 HE and above)

[edit]

Released November 5, 2012.

  • CPU steppings: C0
  • Multi-chip module consisting of two dies, each with fourPiledriver module
  • L2 cache: 4 × 2 MB per die (16 MB total)
  • L3 cache: 2 × 8 MB, shared within each die
  • Clock rate: 1.8 GHz (6366 HE) – 2.8 GHz (6386 SE)
  • 4 × HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link)
  • HT Assist
  • Support for DDR3 1866 MHz memory
  • Turbo CORE support, from 3.1 GHz (6366 HE) to 3.5 GHz (6386 SE)
  • Supports up to quad-processor configurations
  • Socket G34

Opteron X (28 nm bulk) –Jaguar microarchitecture

[edit]
Main article:Jaguar (microarchitecture)

Quad-core –Kyoto (X1150)

[edit]

Released May 29, 2013

  • Single SoC with oneJaguar module and integrated I/O
  • Configurable CPU frequency andTDP
  • L2 cache: 2 MB shared
  • CPU frequency: 1.0–2.0 GHz
  • Max. TDP: 9–17 W
  • Support for DDR3-1600 memory
  • Socket FT3

Quad-core APU –Kyoto (X2150)

[edit]

Released May 29, 2013

  • Single SoC with oneJaguar module, integratedGCN GPU and I/O
  • Configurable CPU/GPU frequency andTDP
  • L2 cache: 2 MB shared
  • CPU frequency: 1.1–1.9 GHz
  • GPU frequency: 266–600 MHz
  • GPU cores: 128
  • Max. TDP: 11–22 W
  • Support for DDR3-1600 memory
  • Socket FT3

Opteron A (28 nm) –ARM Cortex-A57 ARM microarchitecture

[edit]
Main article:ARM Cortex-A57
Main article:ARM architecture

A1100-series

[edit]

The Opteron A1100-series "Seattle" (28 nm) are SoCs based onARM Cortex-A57 cores that use theARMv8-A instruction set. They were first released in January 2016.[12][13]

  • Cores: 4–8
  • Frequency: 1.7–2.0 GHz
  • L2 cache: 2 MB (4 core) or 4 MB (8 core)
  • L3 cache: 8 MB
  • Thermal design power: 25 W (4 core) or 32 W (8 core)
  • Up to 64 GB DDR3L-1600 and up to 128 GB DDR4-1866 with ECC
  • SoC peripherals include 14 × SATA 3, 2 × integrated 10 GbE LAN, and eight PCI Express lanes in ×8, ×4, and ×2 configurations

Opteron X (28 nm bulk) –Excavator microarchitecture

[edit]
Main article:Excavator (microarchitecture)

Released June, 2017

Dual-core –Toronto (X3216)

[edit]
  • L2 cache: 1 MB
  • CPU frequency: 1.6 GHz
  • Turbo CORE support, 3.0 GHz
  • GPU frequency: 800 MHz
  • TDP: 12–15 W
  • Support for DDR4 1600 MHz memory

Quad-core –Toronto (X3418 & X3421)

[edit]
  • L2 cache: 2 × 1 MB
  • CPU frequency: 1.8–2.1 GHz
  • Turbo CORE support, 3.2–3.4 GHz
  • GPU frequency: 800 MHz
  • TDP: 12–35 W
  • Support for DDR4 2400 MHz memory

Supercomputers

[edit]

Opteron processors first appeared in the top 100 systems of thefastest supercomputers in the world list in the early 2000s. By the summer of 2006, 21 of the top 100 systems used Opteron processors, and in the November 2010 and June 2011 lists the Opteron reached its maximum representation of 33 of the top 100 systems. The number of Opteron-based systems decreased fairly rapidly after this peak, falling to 3 of the top 100 systems by November 2016, and in November 2017 only one Opteron-based system remained.[14][15]

Several supercomputers using only Opteron processors were ranked in the top 10 systems between 2003 and 2015, notably:

Other top 10 systems using a combination of Opteron processors andcompute accelerators have included:

The only system remaining on the list (as of November 2017), also using Opteron processors combined with compute accelerators:

Issues

[edit]

Opteron without Optimized Power Management

[edit]

AMD released some Opteron processors without Optimized Power Management (OPM) support, which use DDR memory. The following table describes those processors without OPM.

P-state

freq.

(GHz)

ModelPackage-

socket

Core #TDP

(W)

Manufacturing
process
Part number (OPN)
MaxMin
1.4N/A140Socket 940182.1130 nmOSA140CEP5AT
240OSA240CEP5AU
840OSA840CEP5AV
1.6142OSA142CEP5AT
242OSA242CEP5AU
842OSA842CEP5AV
24285.390 nmOSA242FAA5BL
842OSA842FAA5BM
260255.0OSK260FAA6CB
860OSK860FAA6CC

Opteron recall (2006)

[edit]

AMD recalled some E4 stepping-revision single-core Opteron processors, including ×52 (2.6 GHz) and ×54 (2.8 GHz) models which use DDR memory. The following table describes affected processors, as listed in AMD Opteron ×52 and ×54 Production Notice of 2006.[16]

Max

P-state
freq.(GHz)

Uni-

processor

Dual

processor

Multi-

processor

Package-

socket

2.6152252852Socket 940
2.8N/A254854
2.6152N/ASocket 939
2.8154

The affected processors may produce inconsistent results if three specific conditions occur simultaneously:

  • The execution of floating point-intensive code sequences
  • Elevated processor temperatures
  • Elevated ambient temperatures

A software verification tool for identifying the AMD Opteron processors listed in the above table that may be affected under these specific conditions is available, only to AMDOEM partners.[citation needed] AMD will replace those processors at no charge.[citation needed]

Recognition

[edit]

In the February 2010 issue ofCustom PC (a UK-based computing magazine focused on PC hardware), the AMD Opteron 144 (released in Summer 2005) appeared in the "Hardware Hall of Fame". It was described as "The best overclocker's CPU ever made" due to its low cost and ability to run at speeds far beyond its stock speed. (According toCustom PC, it could run at "close to 3 GHz on air".)

See also

[edit]

References

[edit]
  1. ^De Gelas, Johan (January 14, 2016)."The Silver Lining of the Late AMD Opteron A1100 Arrival".anandtech.com.AnandTech. Archived fromthe original on January 16, 2016. RetrievedSeptember 5, 2020.
  2. ^"SPECint2006 Rate Results for multiprocessor systems". RetrievedDecember 27, 2008.
  3. ^"AMD Introduces the World's Most Advanced x86 Processor, Designed for the Demanding Datacenter".Press release. AMD. September 10, 2007. RetrievedJanuary 6, 2014.
  4. ^"The Inner circuitry of the powerful quad-core AMD processor".Photo. AMD. Archived fromthe original on November 28, 2008. RetrievedJanuary 6, 2011.
  5. ^"Quad-Core Upgradeability". RetrievedMarch 6, 2007.6-core Opteron Processors codenamed 'Istanbul' were announced on July 1, 2009. They were a drop-in upgrade for existing Socket F servers.
  6. ^""HT Assist": What is it, and how does it help?". RetrievedJanuary 2, 2013.
  7. ^Merritt, Rick."AMD tips quad-core performance". EETimes.com. RetrievedMarch 16, 2007.
  8. ^"AMD Opteron X2150 APU". RetrievedOctober 19, 2014.
  9. ^"AMD Transforms Enterprise Computing With AMD Opteron Processor, Eliminating Barriers To 64-Bit Computing" (Press release). AMD. April 22, 2003. Archived fromthe original on February 20, 2006.
  10. ^Hruska, Joel (May 7, 2008)."AMD talks Shanghai performance, features, roadmap to 2010".Ars Technica.
  11. ^abFast Facts AMD[dead link]
  12. ^"Opteron A series".AMD. September 6, 2023. RetrievedSeptember 11, 2023.
  13. ^AMD's first ARM-based processor, the Opteron A1100, is finally here, ExtremeTech, January 14, 2016, retrievedAugust 14, 2016
  14. ^"TOP500 List – November 2016".TOP500. Archived fromthe original on June 26, 2017. RetrievedFebruary 21, 2017.
  15. ^"TOP500 List – November 2017".TOP500. Archived fromthe original on April 5, 2020. RetrievedJanuary 9, 2018.
  16. ^"AMD Opteron Processor Models ×52 and ×54 Production Notice"(PDF) (Press release).Advanced Micro Devices. April 2006. RetrievedNovember 30, 2006.

External links

[edit]
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