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Themedia-independent interface (MII) was originally defined as a standard interface to connect aFast Ethernet (i.e.,100 Mbit/s)medium access control (MAC) block to aPHY chip. The MII is standardized byIEEE 802.3u and connects different types of PHYs to MACs. Beingmedia independent means that different types of PHY devices for connecting to different media (i.e.twisted pair,fiber optic, etc.) can be used without redesigning or replacing the MAC hardware. Thus any MAC may be used with any PHY, independent of the network signal transmission medium.
The MII can be used to connect a MAC to an external PHY using a pluggable connector or directly to a PHY chip on the samePCB. On older PCs theCNR connector Type B carried MII signals.
Network data on the interface isframed using the IEEEEthernet standard. As such it consists of a preamble, start frame delimiter, Ethernet headers, protocol-specific data and acyclic redundancy check (CRC). The original MII transfers network data using 4-bitnibbles in each direction (4 transmit data bits, 4 receive data bits). The data is clocked at 25 MHz to achieve100 Mbit/s throughput. The original MII design has been extended to support reduced signals and increased speeds. The aberration xMII stands for generic media-independent interface, which includes:
TheManagement Data Input/Output (MDIO) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. At power up, usingautonegotiation, the PHY usually adapts to whatever it is connected to unless settings are altered via the MDIO interface.
The standard MII features a small set of registers:[2]: Section 22.2.4 "Management functions"
Register #15 is reserved; registers #16 through #31 are vendor-specific. The registers are used to configure the device and to query the current operating mode.[further explanation needed]
The MII Status Word is the most useful datum, since it may be used to detect whether anEthernet NIC is connected to a network. It contains abit field with the following information:[2]: Section 22.2.4.2.2 "100BASE-X full duplex ability"
| Bit value | Meaning |
|---|---|
| 0x8000 | Capable of100BASE-T4 |
| 0x6000 | Capable of100BASE-TX full/half duplex |
| 0x1800 | Capable of10BASE-T full/half duplex |
| 0x0600 | Capable of100BASE-T2 full/half duplex |
| 0x0100 | Extended status (Gigabit Ethernet) register exists |
| 0x0080 | Capable of unidirectional operation |
| 0x0040 | Management frame preamble suppression permitted |
| 0x0020 | Autonegotiation complete |
| 0x0010 | Remote fault |
| 0x0008 | Capable of Autonegotiation |
| 0x0004 | Link established |
| 0x0002 | Jabber detected |
| 0x0001 | Extended MII registers exist |
| Signal name | Description | Direction |
|---|---|---|
| TX_CLK | Transmit clock | PHY to MAC |
| TXD0 | Transmit data bit 0 (transmitted first) | MAC to PHY |
| TXD1 | Transmit data bit 1 | MAC to PHY |
| TXD2 | Transmit data bit 2 | MAC to PHY |
| TXD3 | Transmit data bit 3 | MAC to PHY |
| TX_EN | Transmit enable | MAC to PHY |
| TX_ER | Transmit error (optional) | MAC to PHY |
The transmit clock is a free-running clock generated by the PHY based on the link speed (25 MHz for100 Mbit/s, 2.5 MHz for10 Mbit/s). The remaining transmit signals are driven by the MAC synchronously on the rising edge of TX_CLK. This arrangement allows the MAC to operate without having to be aware of the link speed. The transmit enable signal is held high during frame transmission and low when the transmitter is idle.
Transmit error may be raised for one or more clock periods during frame transmission to request the PHY to deliberately corrupt the frame in some visible way that precludes it from being received as valid. This may be used to abort a frame when some problem is detected after transmission has already started. The MAC may omit the signal if it has no use for this functionality, in which case the signal should be tied low for the PHY.
More recently, raising transmit erroroutside frame transmission is used to indicate the transmit data lines are being used for special-purpose signalling. Specifically, the data value 0b0001 (held continuously with TX_EN low and TX_ER high) is used to request anEEE-capable PHY to enter low power mode.
| Signal name | Description | Direction |
|---|---|---|
| RX_CLK | Receive clock | PHY to MAC |
| RXD0 | Receive data bit 0 (received first) | PHY to MAC |
| RXD1 | Receive data bit 1 | PHY to MAC |
| RXD2 | Receive data bit 2 | PHY to MAC |
| RXD3 | Receive data bit 3 | PHY to MAC |
| RX_DV | Receive data valid | PHY to MAC |
| RX_ER | Receive error | PHY to MAC |
| CRS | Carrier sense | PHY to MAC |
| COL | Collision detect | PHY to MAC |
The first seven receiver signals are entirely analogous to the transmitter signals, except RX_ER is not optional and used to indicate the received signal could not be decoded to valid data. The receive clock is recovered from the incoming signal during frame reception. When no clock can be recovered (i.e. when the medium is silent), the PHY must present a free-running clock as a substitute.
The receive data valid signal (RX_DV) is not required to go high immediately when the frame starts, but must do so in time to ensure the "start of frame delimiter" byte is included in the received data. Some of the preamble nibbles may be lost.
Similar to transmit, raising RX_ER outside a frame is used for special signaling. For receive, two data values are defined: 0b0001 to indicate the link partner is in EEE low power mode, and 0b1110 for afalse carrier indication.
The CRS and COL signals are asynchronous to the receive clock, and are only meaningful in half-duplex mode. Carrier sense is high when transmitting, receiving, or the medium is otherwise sensed as being in use. If a collision is detected, COL also goes high while the collision persists.
In addition, the MAC may weakly pull-up the COL signal, allowing the combination of COL high with CRS low (which a PHY will never produce) to serve as indication of an absent/disconnected PHY.
| Signal name | Description | Direction |
|---|---|---|
| MDIO | Management data | Bidirectional |
| MDC | Management data clock | MAC to PHY |
MDC and MDIO constitute a synchronous serial data interface similar toI²C. As with I²C, the interface is amultidrop bus so MDC and MDIO can be shared among multiple PHYs.
The interface requires 18 signals, out of which only two (MDIO and MDC) can be shared among multiple PHYs. This presents a problem, especially for multiport devices; for example, an eight-port switch using MII would need 8 × 16 + 2 = 130 signals.
Reduced media-independent interface (RMII) is a standard which was developed to reduce the number of signals required to connect a PHY to a MAC. This helps reduce cost and complexity for network hardware, especially in the context ofmicrocontrollers with built-in MAC,FPGAs, multiport switches or repeaters, and PC motherboard chipsets. The following changes from the MII standard cut the number of required signals from 18 in half to only 9:
Additionally on multiport devices (such as a switch), MDIO, MDC, and REF_CLK may be shared, leaving 6 or 7 pins per port.
| Signal name | Description | Direction |
|---|---|---|
| REF_CLK | Continuous 50 MHz reference clock | Reference clock may be an input on both devices from an external clock source, or may be driven from the MAC to the PHY, or may be driven from the PHY to the MAC |
| TXD0 | Transmit data bit 0 (transmitted first) | MAC to PHY |
| TXD1 | Transmit data bit 1 | MAC to PHY |
| TX_EN | When high, clock data on TXD0 and TXD1 to the transmitter | MAC to PHY |
| RXD0 | Receive data bit 0 (received first) | PHY to MAC |
| RXD1 | Receive data bit 1 | PHY to MAC |
| CRS_DV | Carrier Sense (CRS) and RX_Data Valid (RX_DV) multiplexed on alternate clock cycles. In10 Mbit/s mode, it alternates every 10 clock cycles. | PHY to MAC |
| RX_ER | Receive error (optional) | PHY to MAC |
| MDIO | Management data | Bidirectional |
| MDC | Management data clock. | MAC to PHY |
Note: the REF_CLK operates at 50 MHz in both100 Mbit/s mode and10 Mbit/s mode. The transmitting side (PHY or MAC) must keep all signals valid for 10 clock cycles in10 Mbit/s mode. The receiver (PHY or MAC) samples the input signals only every 10 cycles in10 Mbit/s mode.
There is no signal which defines whether the interface is in full or half duplex mode, but both the MAC and the PHY need to agree. This must instead be communicated over the serial MDIO/MDC interface. There is also no signal which defines whether the interface is in 10 or100 Mbit/s mode, so this must also be handled using the MDIO/MDC interface. Version 1.2 of the RMII Consortium specification states that its MDIO/MDC interface is identical to that specified for MII in IEEE 802.3u. Current revisions of IEEE 802.3 specify a standard MDIO/MDC mechanism for negotiating and configuring the link's speed and duplex mode, but it is possible that older PHY devices might have been designed against obsolete versions of the standard, and may therefore use proprietary methods to set speed and duplex.
The lack of the RX_ER signal which is not connected on some MACs (such as multiport switches) is dealt with by data replacement on some PHYs to invalidate theCRC. The missing COL signal is derived from AND-ing together the TX_EN and the decoded CRS signal from the CRS_DV line in half duplex mode. This means a slight modification of the definition of CRS: On MII, CRS is asserted for both Rx and Tx frames; on RMII only for Rx frames. This has the consequence that on RMII the two error conditionsno carrier andlost carrier cannot be detected, and it is difficult or impossible to support shared media such as10BASE2 or10BASE5.
Since the RMII standard neglected to stipulate that TX_EN should only be sampled on alternate clock cycles, it is not symmetric with CRS_DV and two RMII PHY devices cannot be connected back to back to form a repeater; this is possible, however, with the National DP83848 which supplies the decoded RX_DV as a supplemental signal in RMII mode.[3]
TTLlogic levels are used for5 V or3.3 V logic. Input high threshold is2.0 V and low is0.8 V. The specification states that inputs should be5 V tolerant, however, some popular chips with RMII interfaces are not5 V tolerant.[citation needed] Newer devices may support2.5 V and1.8 V logic.[citation needed]
The RMII signals are treated aslumped signals rather thantransmission lines. However, the IEEE version of the related MII standard specifies68 Ω trace impedance.[4] National recommends running50 Ω traces with33 Ωseries termination resistors for either MII or RMII mode to reduce reflections.[citation needed] National also suggests that traces be kept under0.15 m long and matched within0.05 m on length to minimize skew.[4]: 5
The gigabit media-independent interface (GMII) is an interface between themedium access control (MAC) device and the physical layer (PHY). The interface operates at speeds up to1000 Mbit/s, implemented using a data interface clocked at 125 MHz with separate eight-bit data paths for receive and transmit, and is backwards compatible with the MII specification and can operate on fall-back speeds of 10 or100 Mbit/s.
The GMII interface was first defined for 1000BASE-X in IEEE 802.3z-1998 as clause 35, and subsequently incorporated into IEEE 802.3-2000 onwards.[2]: Clause 35
| Signal name | Description |
|---|---|
| GTXCLK | Clock signal for gigabit TX signals (125 MHz) |
| TXCLK | Clock signal for10/100 Mbit/s signals |
| TXD[7..0] | Data to be transmitted |
| TXEN | Transmitter enable |
| TXER | Transmitter error (used to intentionally corrupt a packet, if necessary) |
There are two transmitter clocks. The clock used depends on whether the PHY is operating at gigabit or10/100 Mbit/s speeds. For gigabit operation, the GTXCLK is supplied to the PHY and the TXD, TXEN, TXER signals are synchronized to this. For 10 or100 Mbit/s operation, the TXCLK is supplied by the PHY and is used for synchronizing those signals. This operates at either 25 MHz for100 Mbit/s or 2.5 MHz for10 Mbit/s connections. In contrast, the receiver uses a single clock signal recovered from the incoming data.
| Signal name | Description |
|---|---|
| RXCLK | Receivedclock signal (recovered from incoming received data) |
| RXD[7..0] | Received data |
| RXDV | Signifies data received is valid |
| RXER | Signifies data received has errors |
| COL | Collision detect (half-duplex connections only) |
| CS | Carrier sense (half-duplex connections only) |
| Signal name | Description |
|---|---|
| MDC | Management interface clock |
| MDIO | Management interface I/O bidirectional pin. |
The management interface controls the behavior of the PHY. It has the same set of registers as the MII, except that register #15 is the Extended Status register.[2]: Section 22.2.4 "Management functions"
| [Mbit/s] | [MHz] | Bits/clock cycle |
|---|---|---|
| 10 | 2.5 | 4 |
| 100 | 25 | 4 |
| 1000 | 125 | 8 |
The reduced gigabit media-independent interface (RGMII) uses half the number of data pins as are used in the GMII interface. This reduction is achieved by running half as many data lines at double speed, time multiplexing signals and by eliminating non-essential carrier-sense and collision-indication signals. Thus RGMII consists only of 14 pins, as opposed to GMII's 24 to 27.
Data is clocked on rising and falling edges for1000 Mbit/s, and on rising edges only for10/100 Mbit/s.[5] The RX_CTL signal carries RXDV (data valid) on the rising edge, and (RXDV xor RXER) on the falling edge. The TX_CTL signal likewise carries TXEN on rising edge and (TXEN xor TXER) on the falling edge. This is the case for both1000 Mbit/s and10/100 Mbit/s.[6]
The transmit clock signal is always provided by the MAC on the TXC line. The receive clock signal is always provided by the PHY on the RXC line.[citation needed]Source-synchronous clocking is used: the clock signal that is output (by either the PHY or the MAC) is synchronous with the data signals. This requires the PCB to be designed to add a 1.5–2 ns delay to the clock signal to meet the setup and hold times on the sink. RGMII v2.0 specifies an optional internal delay, obviating the need for the PCB designer to add delay; this is known as RGMII-ID.
| Signal name | Description | Direction |
|---|---|---|
| TXC | Clock signal | MAC to PHY |
| TXD[3..0] | Data to be transmitted | MAC to PHY |
| TX_CTL | Multiplexing of transmitter enable and transmitter error | MAC to PHY |
| RXC | Receivedclock signal (recovered from incoming received data) | PHY to MAC |
| RXD[3..0] | Received data | PHY to MAC |
| RX_CTL | Multiplexing of data received is valid and receiver error | PHY to MAC |
| MDC | Management interface clock | MAC to PHY |
| MDIO | Management interface I/O | Bidirectional |
RGMII version 1.3[7] uses 2.5V CMOS,[8] whereas RGMII version 2 uses 1.5VHSTL.[9]
The serial gigabit media-independent interface (SGMII) is a variant of MII used forGigabit Ethernet but can also carry10/100 Mbit/s Ethernet.
It uses differential pairs at 625 MHz clock frequency DDR for TX and RX data and TX and RX clocks. It differs fromGMII by its low-power and low pin-count8b/10b-codedSerDes. Transmit and receive path each use one differential pair for data and another differential pair for clock. The TX/RX clocks must be generated on device output but are optional on device input (clock recovery may be used alternatively).10/100 Mbit/s Ethernet is carried by duplicating data words 100/10 times each, so the clock is always at 625 MHz.
The high serial gigabit media-independent interface (HSGMII) is functionally similar to the SGMII but supports link speeds of up to2.5 Gbit/s. Sometimes this interface is also called OCSGMII (overclocked SGMII).[10]
The quad serial gigabit media-independent interface (QSGMII) is a method of combining four SGMII lines into a5 Gbit/s interface. QSGMII, like SGMII, useslow-voltage differential signaling (LVDS) for the TX and RX data, and a single LVDS clock signal. QSGMII uses significantly fewer signal lines than four separate SGMII connections.
QSGMII predatesNBASE-T and is used to connect multi-port PHYs to MACs, for example in network routers.[11]
The PSGMII (penta serial gigabit media-independent interface) uses the same signal lines as QSGMII, but operates at6.25 Gbit/s, which supports five 1 gigabit/s ports through one MII.
![[icon]](/mt/?noimg=&dark=on&url=https%3a%2f%2fen.m.wikipedia.org%2fwiki%2fFile%3aWiki_letter_w_cropped.svg) | This sectionneeds expansion with: signal description. You can help byadding missing information.(July 2023) |
10 gigabit media-independent interface (XGMII) is a standard defined inIEEE 802.3 designed for connecting full duplex10 Gigabit Ethernet (10GbE) ports to each other and to other electronic devices on aprinted circuit board (PCB). It is now typically used for on-chip connections. PCB connections are now mostly accomplished withXAUI. XGMII features two 32-bit datapaths (Rx & Tx) and two four-bit control flows (Rxc and Txc), operating at 156.25 MHzDDR (312.5 MT/s).[12]
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