This is alist of interface bit rates, a measure ofinformation transfer rates, ordigital bandwidth capacity, at which digital interfaces in acomputer ornetwork can communicate over various kinds ofbuses andchannels. The distinction can be arbitrary between acomputer bus, often closer in space, and largertelecommunications networks. Many deviceinterfaces orprotocols (e.g., SATA, USB,SAS,PCIe) are used both inside many-device boxes, such as a PC, and one-device-boxes, such as ahard drive enclosure. Accordingly, this page lists both the internal ribbon and external communications cable standards together in one sortable table.

Most of the listed rates are theoretical maximumthroughput measures; in practice, theactual effective throughput is almost inevitably lower in proportion to the load from other devices (network/bus contention), physical or temporal distances, and otheroverhead indata link layer protocols etc. The maximumgoodput (for example, the file transfer rate) may be even lower due to higher layer protocol overhead and data packet retransmissions caused by linenoise orinterference such ascrosstalk, or lost packets incongested intermediate network nodes. All protocols lose something, and the more robust ones that deal resiliently with very many failure situations tend to lose more maximum throughput to get higher total long-term rates.

Device interfaces where one bus transfers data via another will be limited to the throughput of the slowest interface, at best. For instance,SATA revision 3.0 (6 Gbit/s) controllers on one PCI Express 2.0 (5 Gbit/s) channel will be limited to the5 Gbit/s rate and have to employ more channels to get around this problem. Early implementations of new protocols very often have this kind of problem. The physical phenomena on which the device relies (such as spinning platters in a hard drive) will also impose limits; for instance, no spinning platter shipping in 2009 saturates SATA revision 2.0 (3 Gbit/s), so moving from this3 Gbit/s interface toUSB 3.0 at4.8 Gbit/s for one spinning drive will result in no increase in realized transfer rate.

Contention in a wireless or noisy spectrum, where the physical medium is entirely out of the control of those who specify the protocol, requires measures that also use up throughput. Wireless devices,BPL, andmodems may produce a higherline rate orgross bit rate, due toerror-correcting codes and otherphysical layer overhead. It is extremely common for throughput to be far less than half of theoretical maximum, though the more recent technologies (notably BPL) employ preemptive spectrum analysis to avoid this and so have much more potential to reach actual gigabit rates in practice than prior modems.

Another factor reducing throughput is deliberate policy decisions made byInternet service providers that are made for contractual, risk management, aggregation saturation, or marketing reasons. Examples arerate limiting,bandwidth throttling, and the assignment ofIP addresses to groups. These practices tend to minimize the throughput available to every user, but maximize the number of users that can be supported on one backbone.

Furthermore, chips are often not available in order to implement the fastest rates.AMD, for instance, does not support the 32-bitHyperTransport interface on any CPU it has shipped as of the end of 2009. Additionally,WiMAX service providers in the US typically support only up to4 Mbit/s as of the end of 2009.

Choosing service providers or interfaces based on theoretical maxima is unwise, especially for commercial needs. A good example is large scale data centers, which should be more concerned with price per port to support the interface, wattage and heat considerations, and total cost of the solution. Because some protocols such as SCSI and Ethernet now operate many orders of magnitude faster than when originally deployed, scalability of the interface is one major factor, as it prevents costly shifts to technologies that are not backward compatible. Underscoring this is the fact that these shifts often happen involuntarily or by surprise, especially when a vendor abandons support for a proprietary system.

By convention, bus and network data rates are denoted either inbits per second –bit/s,kbit/s (10³ bit/s),Mbit/s (10⁶ bit/s),Gbit/s (10⁹ bit/s),Tbit/s (10¹² bit/s) – orbytes per second –B/s,kB/s (10³ B/s),MB/s (10⁶ B/s),GB/s (10⁹ B/s),TB/s (10¹² B/s). In general,parallel interfaces are quoted inB/s andserial inbit/s. The more commonly used is shown below inbold type.

On devices likemodems, bytes may be more than 8 bits long because they may be individually padded out with additional start and stop bits; the figures below will reflect this. Where channels useline codes (such asEthernet,Serial ATA, andPCI Express), quoted rates are for the decoded signal.

The figures below aresimplex data rates, which may conflict with the duplex rates vendors sometimes use in promotional materials. Where two values are listed, the first value is thedownstream rate and the second value is the upstream rate.

The use ofdecimal prefixes is standard in data communications.

The figures below are grouped by network or bus type, then sorted within each group from lowest to highest bandwidth; gray shading indicates a lack of known implementations.

As stated above, all quoted bandwidths are for each direction. Therefore, forduplex interfaces (capable of simultaneous transmission both ways), the stated values aresimplex (one way) speeds, rather than total upstream+downstream.

Time signal station toradio clock

802.11 networks in infrastructure mode are half-duplex; all stations share the medium. In infrastructure or access point mode, all traffic has to pass through anAccess Point (AP). Thus, two stations on the same access point that are communicating with each other must have each and every frame transmitted twice: from the sender to the access point, then from the access point to the receiver. This approximately halves the effective bandwidth.

802.11 networks in ad hoc mode are still half-duplex, but devices communicate directly rather than through an access point. In this mode all devices must be able tosee each other, instead of only having to be able tosee the access point.

^x LPC protocol includes high overhead. While the gross data rate equals 33.3 million 4-bit-transfers per second (or16.67 MB/s), the fastest transfer, firmware read, results in15.63 MB/s. The next fastest bus cycle, 32-bit ISA-style DMA write, yields only6.67 MB/s. Other transfers may be as low as2 MB/s.^[43]

^y Uses128b/130b encoding, meaning that about 1.54% of each transfer is used for error detection instead of carrying data between the hardware components at each end of the interface. For example, a single link PCIe 3.0 interface has an8 Gbit/s transfer rate, yet its usable bandwidth is only about7.88 Gbit/s.

^z Uses8b/10b encoding, meaning that 20% of each transfer is used by the interface instead of carrying data from between the hardware components at each end of the interface. For example, a single link PCIe 1.0 has a2.5 Gbit/s transfer rate, yet its usable bandwidth is only2 Gbit/s (250 MB/s).

^w UsesPAM-4 encoding and a 256 bytesFLIT block, of which 14 bytes areFEC andCRC, meaning that 5.47% of total data rate is used for error detection and correction instead of carrying data. For example, a single link PCIe 6.0 interface has a64 Gbit/s total transfer rate, yet its usable bandwidth is only60.5 Gbit/s.

^a Uses8b/10b encoding^b Uses64b/66b encoding^c Uses 128b/150b encoding

The table below shows values forPC memory module types.These modules usually combine multiple chips on onecircuit board.SIMM modules connect to the computer via an 8-bit- or 32-bit-wide interface. RIMM modules used byRDRAM are 16-bit- or 32-bit-wide.^[50]DIMM modules connect to the computer via a 64-bit-wide interface.Some other computer architectures use different modules with a different bus width.

In a single-channel configuration, only one module at a time can transfer information to the CPU.In multi-channel configurations, multiple modules can transfer information to the CPU at the same time, in parallel.FPM,EDO,SDR, andRDRAM memory was not commonly installed in a dual-channel configuration.DDR andDDR2 memory is usually installed in single- or dual-channel configuration.DDR3 memory is installed in single-, dual-, tri-, and quad-channel configurations.Bit rates of multi-channel configurations are the product of the module bit-rate (given below) and the number of channels.