Incomputer science, aninstruction set architecture (ISA) is anabstract model that generally defines howsoftware controls theCPU in a computer or a family of computers.^[1] A device or program that executes instructions described by that ISA, such as a central processing unit (CPU), is called animplementation of that ISA.

In general, an ISA defines the supportedinstructions,data types,registers, the hardware support for managingmain memory,^{[clarification needed]} fundamental features (such as thememory consistency,addressing modes,virtual memory), and theinput/output model of implementations of the ISA.

An ISA specifies the behavior ofmachine code running on implementations of that ISA in a fashion that does not depend on the characteristics of that implementation, providingbinary compatibility between implementations. This enables multiple implementations of an ISA that differ in characteristics such asperformance, physical size, and monetary cost (among other things), but that are capable of running the same machine code, so that a lower-performance, lower-cost machine can be replaced with a higher-cost, higher-performance machine without having to replace software. It also enables the evolution of themicroarchitectures of the implementations of that ISA, so that a newer, higher-performance implementation of an ISA can run software that runs on previous generations of implementations.

If anoperating system maintains a standard and compatibleapplication binary interface (ABI) for a particular ISA, machine code will run on future implementations of that ISA and operating system. However, if an ISA supports running multiple operating systems, it does not guarantee that machine code for one operating system will run on another operating system, unless the first operating system supports running machine code built for the other operating system.

An ISA can be extended by adding instructions or other capabilities, or adding support for larger addresses and data values; an implementation of the extended ISA will still be able to executemachine code for versions of the ISA without those extensions. Machine code using those extensions will only run on implementations that support those extensions.

The binary compatibility that they provide makes ISAs one of the most fundamental abstractions incomputing.

An instruction set architecture is distinguished from amicroarchitecture, which is the set ofprocessor design techniques used, in a particular processor, to implement the instruction set. Processors with different microarchitectures can share a common instruction set. For example, theIntelPentium and theAMDAthlon implement nearly identical versions of thex86 instruction set, but they have radically different internal designs.

The concept of anarchitecture, distinct from the design of a specific machine, was developed byFred Brooks at IBM during the design phase ofSystem/360.

Prior to NPL [System/360], the company's computer designers had been free to honor cost objectives not only by selecting technologies but also by fashioning functional and architectural refinements. The SPREAD compatibility objective, in contrast, postulated a single architecture for a series of five processors spanning a wide range of cost and performance. None of the five engineering design teams could count on being able to bring about adjustments in architectural specifications as a way of easing difficulties in achieving cost and performance objectives.^[2]: p.137

Somevirtual machines that supportbytecode as their ISA such asSmalltalk, theJava virtual machine, andMicrosoft'sCommon Language Runtime, implement this by translating the bytecode for commonly used code paths into native machine code. In addition, these virtual machines execute less frequently used code paths by interpretation (see:Just-in-time compilation).Transmeta implemented the x86 instruction set atopvery long instruction word (VLIW) processors in this fashion.

An ISA may be classified in a number of different ways. A common classification is by architecturalcomplexity. Acomplex instruction set computer (CISC) has many specialized instructions, some of which may only be rarely used in practical programs. Areduced instruction set computer (RISC) simplifies the processor by efficiently implementing only the instructions that are frequently used in programs, while the less common operations are implemented as subroutines, having their resulting additional processor execution time offset by infrequent use.^[3]

Other types includeVLIW architectures, and the closely relatedlong instruction word (LIW)^{[citation needed]} andexplicitly parallel instruction computing (EPIC) architectures. These architectures seek to exploitinstruction-level parallelism with less hardware than RISC and CISC by making thecompiler responsible for instruction issue and scheduling.^[4]

Architectures with even less complexity have been studied, such as theminimal instruction set computer (MISC) andone-instruction set computer (OISC). These are theoretically important types, but have not been commercialized.^[5][6]

Machine language is built up from discretestatements orinstructions. On the processing architecture, a given instruction may specify:

• opcode (the instruction to be performed) e.g. add, copy, test
• any explicit operands:

registers

literal/constant values

addressing modes used to access memory

More complex operations are built up by combining these simple instructions, which are executed sequentially, or as otherwise directed bycontrol flow instructions.

Examples of operations common to many instruction sets include:

• Set aregister to a fixed constant value.
• Copy data from a memory location or a register to a memory location or a register (a machine instruction is often calledmove; however, the term is misleading). They are used to store the contents of a register, the contents of another memory location or the result of a computation, or to retrieve stored data to perform a computation on it later. They are often calledload orstore operations.
• Read orwrite data from hardware devices.

• Add,subtract,multiply, ordivide the values of two registers, placing the result in a register, possibly setting one or morecondition codes in astatus register.^[7]
  • increment,decrement in some ISAs, saving operand fetch in trivial cases.
• Performbitwise operations, e.g., taking theconjunction anddisjunction of corresponding bits in a pair of registers, taking thenegation of each bit in a register.
• Compare two values in registers (for example, to see if one is less, or if they are equal).
• Floating-point instructions for arithmetic on floating-point numbers.^[7]

• Branch to another location in the program and execute instructions there.
• Conditionally branch to another location if a certain condition holds.
• Indirectly branch to another location.
• Skip one of more instructions, depending on conditions
• Trap Explicitly cause aninterrupt, either conditionally or unconditionally.
• Call another block of code, while saving, e.g., the location of the next instruction, as a point to return to.

• Load/store data to and from a coprocessor or exchanging with CPU registers.
• Perform coprocessor operations.

Processors may include "complex" instructions in their instruction set. A single "complex" instruction does something that may take many instructions on other computers. Such instructions aretypified by instructions that take multiple steps, control multiple functional units, or otherwise appear on a larger scale than the bulk of simple instructions implemented by the given processor. Some examples of "complex" instructions include:

• transferring multiple registers to or from memory (especially thestack) at once
• moving large blocks of memory (e.g.string copy orDMA transfer)
• complicated integer andfloating-point arithmetic (e.g.square root, ortranscendental functions such aslogarithm,sine,cosine, etc.)
• SIMD instructions, a single instruction performing an operation on many homogeneous values in parallel, possibly in dedicatedSIMD registers
• performing an atomictest-and-set instruction or otherread–modify–writeatomic instruction
• instructions that performALU operations with an operand from memory rather than a register

Complex instructions are more common in CISC instruction sets than in RISC instruction sets, but RISC instruction sets may include them as well. RISC instruction sets generally do not include ALU operations with memory operands, or instructions to move large blocks of memory, but most RISC instruction sets includeSIMD orvector instructions that perform the same arithmetic operation on multiple pieces of data at the same time. SIMD instructions have the ability of manipulating large vectors and matrices in minimal time. SIMD instructions allow easyparallelization of algorithms commonly involved in sound, image, and video processing. Various SIMD implementations have been brought to market under trade names such asMMX,3DNow!, andAltiVec.

On traditional architectures, an instruction includes anopcode that specifies the operation to perform, such asadd contents of memory to register—and zero or moreoperand specifiers, which may specifyregisters, memory locations, or literal data. The operand specifiers may haveaddressing modes determining their meaning or may be in fixed fields. Invery long instruction word (VLIW) architectures, which include manymicrocode architectures, multiple simultaneous opcodes and operands are specified in a single instruction.

Some exotic instruction sets do not have an opcode field, such astransport triggered architectures (TTA), only operand(s).

Moststack machines have "0-operand" instruction sets in which arithmetic and logical operations lack any operand specifier fields; only instructions that push operands onto the evaluation stack or that pop operands from the stack into variables have operand specifiers. The instruction set carries out most ALU actions with postfix (reverse Polish notation) operations that work only on the expressionstack, not on data registers or arbitrary main memory cells. This can be very convenient for compiling high-level languages, because most arithmetic expressions can be easily translated into postfix notation.^[8]

Conditional instructions often have a predicate field—a few bits that encode the specific condition to cause an operation to be performed rather than not performed. For example, a conditional branch instruction will transfer control if the condition is true, so that execution proceeds to a different part of the program, and not transfer control if the condition is false, so that execution continues sequentially. Some instruction sets also have conditional moves, so that the move will be executed, and the data stored in the target location, if the condition is true, and not executed, and the target location not modified, if the condition is false. Similarly, IBMz/Architecture has a conditional store instruction. A few instruction sets include a predicate field in every instruction. Having predicates for non-branch instructions is calledpredication.

Instruction sets may be categorized by the maximum number of operandsexplicitly specified in instructions.

(In the examples that follow,a,b, andc are (direct or calculated) addresses referring to memory cells, whilereg1 and so on refer to machine registers.)

C = A+B

• 0-operand (zero-address machines), so calledstack machines: All arithmetic operations take place using the top one or two positions on the stack:^[9]push a,push b,add,pop c.
  • C = A+B needsfour instructions.^[10] For stack machines, the terms "0-operand" and "zero-address" apply to arithmetic instructions, but not to all instructions, as 1-operand push and pop instructions are used to access memory.
• 1-operand (one-address machines), so calledaccumulator machines, include early computers and many smallmicrocontrollers: most instructions specify a single right operand (that is, constant, a register, or a memory location), with the implicitaccumulator as the left operand (and the destination if there is one):load a,add b,store c.
  • C = A+B needsthree instructions.^[10]
• 2-operand — many CISC and RISC machines fall under this category:
  • CISC —move A toC; thenadd B toC.
    • C = A+B needstwo instructions. This effectively 'stores' the result without an explicitstore instruction.
  • CISC — Often machines arelimited to one memory operand per instruction:load a,reg1;add b,reg1;store reg1,c; This requires a load/store pair for any memory movement regardless of whether theadd result is an augmentation stored to a different place, as inC = A+B, or the same memory location:A = A+B.
    • C = A+B needsthree instructions.
  • RISC — Requiring explicit memory loads, the instructions would be:load a,reg1;load b,reg2;add reg1,reg2;store reg2,c.
    • C = A+B needsfour instructions.
• 3-operand, allowing better reuse of data:^[11]
  • CISC — It becomes either a single instruction:add a,b,c
    • C = A+B needsone instruction.
  • CISC — Or, on machines limited to two memory operands per instruction,move a,reg1;add reg1,b,c;
    • C = A+B needstwo instructions.
  • RISC — arithmetic instructions use registers only, so explicit 2-operand load/store instructions are needed:load a,reg1;load b,reg2;add reg1+reg2->reg3;store reg3,c;
    • C = A+B needsfour instructions.
    • Unlike 2-operand or 1-operand, this leaves all three values a, b, and c in registers available for further reuse.^[11]
• more operands—some CISC machines permit a variety of addressing modes that allow more than 3 operands (registers or memory accesses), such as theVAX "POLY" polynomial evaluation instruction.

Due to the large number of bits needed to encode the three registers of a 3-operand instruction, RISC architectures that have 16-bit instructions are invariably 2-operand designs, such as the Atmel AVR,TI MSP430, and some versions ofARM Thumb. RISC architectures that have 32-bit instructions are usually 3-operand designs, such as theARM,AVR32,MIPS,Power ISA, andSPARC architectures.

Each instruction specifies some number of operands (registers, memory locations, or immediate values)explicitly. Some instructions give one or both operands implicitly, such as by being stored on top of thestack or in an implicit register. If some of the operands are given implicitly, fewer operands need be specified in the instruction. When a "destination operand" explicitly specifies the destination, an additional operand must be supplied. Consequently, the number of operands encoded in an instruction may differ from the mathematically necessary number of arguments for a logical or arithmetic operation (thearity). Operands are either encoded in the "opcode" representation of the instruction, or else are given as values or addresses following the opcode.

Register pressure measures the availability of free registers at any point in time during the program execution. Register pressure is high when a large number of the available registers are in use; thus, the higher the register pressure, the more often the register contents must bespilled into memory. Increasing the number of registers in an architecture decreases register pressure but increases the cost.^[12]

While embedded instruction sets such asThumb suffer from extremely high register pressure because they have small register sets, general-purpose RISC ISAs likeMIPS andAlpha enjoy low register pressure. CISC ISAs like x86-64 offer low register pressure despite having smaller register sets. This is due to the many addressing modes and optimizations (such as sub-register addressing, memory operands in ALU instructions, absolute addressing, PC-relative addressing, and register-to-register spills) that CISC ISAs offer.^[13]

The size or length of an instruction varies widely, from as little as four bits in somemicrocontrollers to many hundreds of bits in someVLIW systems. Processors used inpersonal computers,mainframes, andsupercomputers have minimum instruction sizes between 8 and 64 bits. The longest possible instruction on x86 is 15 bytes (120 bits).^[14] Within an instruction set, different instructions may have different lengths. In some architectures, notably mostreduced instruction set computers (RISC),instructions are a fixed length, typically corresponding with that architecture'sword size. In other architectures, instructions havevariable length, typically integral multiples of abyte or ahalfword. Some, such as theARM withThumb-extension havemixed variable encoding, that is two fixed, usually 32-bit and 16-bit encodings, where instructions cannot be mixed freely but must be switched between on a branch (or exception boundary in ARMv8).

Fixed-length instructions are less complicated to handle than variable-length instructions for several reasons (not having to check whether an instruction straddles a cache line or virtual memory page boundary,^[11] for instance), and are therefore somewhat easier to optimize for speed.

In early 1960s computers, main memory was expensive and very limited, even on mainframes. Minimizing the size of a program to make sure it would fit in the limited memory was often central. Thus the size of the instructions needed to perform a particular task, thecode density, was an important characteristic of any instruction set. It remained important on the initially-tiny memories of minicomputers and then microprocessors. Density remains important today, for smartphone applications, applications downloaded into browsers over slow Internet connections, and in ROMs for embedded applications. A more general advantage of increased density is improved effectiveness of caches and instruction prefetch.

Computers with high code density often have complex instructions for procedure entry, parameterized returns, loops, etc. (therefore retroactively namedComplex Instruction Set Computers,CISC). However, more typical, or frequent, "CISC" instructions merely combine a basic ALU operation, such as "add", with the access of one or more operands in memory (usingaddressing modes such as direct, indirect, indexed, etc.). Certain architectures may allow two or three operands (including the result) directly in memory or may be able to perform functions such as automatic pointer increment, etc. Software-implemented instruction sets may have even more complex and powerful instructions.

Reduced instruction-set computers,RISC, were first widely implemented during a period of rapidly growing memory subsystems. They sacrifice code density to simplify implementation circuitry, and try to increase performance via higher clock frequencies and more registers. A single RISC instruction typically performs only a single operation, such as an "add" of registers or a "load" from a memory location into a register. A RISC instruction set normally has a fixedinstruction length, whereas a typical CISC instruction set has instructions of widely varying length. However, as RISC computers normally require more and often longer instructions to implement a given task, they inherently make less optimal use of bus bandwidth and cache memories.

Certain embedded RISC ISAs likeThumb andAVR32 typically exhibit very high density owing to a technique called code compression. This technique packs two 16-bit instructions into one 32-bit word, which is then unpacked at the decode stage and executed as two instructions.^[15]

Minimal instruction set computers (MISC) are commonly a form ofstack machine, where there are few separate instructions (8–32), so that multiple instructions can be fit into a single machine word. These types of cores often take little silicon to implement, so they can be easily realized in an FPGA (field-programmable gate array) or in amulti-core form. The code density of MISC is similar to the code density of RISC; the increased instruction density is offset by requiring more of the primitive instructions to do a task.^{[16][failed verification]}

There has been research intoexecutable compression as a mechanism for improving code density. The mathematics ofKolmogorov complexity describes the challenges and limits of this.

In practice, code density is also dependent on thecompiler. Mostoptimizing compilers have options that control whether to optimize code generation for execution speed or for code density. For instanceGCC has the option-Os to optimize for small machine code size, and-O3 to optimize for execution speed at the cost of larger machine code.

The instructions constituting a program are rarely specified using their internal, numeric form (machine code); they may be specified by programmers using anassembly language or, more commonly, may be generated fromhigh-level programming languages bycompilers.^[17]

The design of instruction sets is a complex issue. There were two stages in history for the microprocessor. The first was the CISC (complex instruction set computer), which had many different instructions. In the 1970s, however, places like IBM did research and found that many instructions in the set could be eliminated. The result was the RISC (reduced instruction set computer), an architecture that uses a smaller set of instructions. A simpler instruction set may offer the potential for higher speeds, reduced processor size, and reduced power consumption. However, a more complex set may optimize common operations, improve memory andcache efficiency, or simplify programming.

Some instruction set designers reserve one or more opcodes for some kind ofsystem call orsoftware interrupt. For example,MOS Technology 6502 uses 00_H,Zilog Z80 uses the eight codes C7,CF,D7,DF,E7,EF,F7,FF_H^[18] whileMotorola 68000 use codes in the range 4E40_H-4E4F_H.^[19]

Fast virtual machines are much easier to implement if an instruction set meets thePopek and Goldberg virtualization requirements.^{[clarification needed]}

TheNOP slide used in immunity-aware programming is much easier to implement if the "unprogrammed" state of the memory is interpreted as aNOP.^{[dubious –discuss]}

On systems with multiple processors,non-blocking synchronization algorithms are much easier to implement^{[citation needed]} if the instruction set includes support for something such as "fetch-and-add", "load-link/store-conditional" (LL/SC), or "atomiccompare-and-swap".

A given instruction set can be implemented in a variety of ways. All ways of implementing a particular instruction set provide the sameprogramming model, and all implementations of that instruction set are able to run the same executables. The various ways of implementing an instruction set give different tradeoffs between cost, performance, power consumption, size, etc.

When designing themicroarchitecture of a processor, engineers use blocks of "hard-wired" electronic circuitry (often designed separately) such as adders, multiplexers, counters, registers, ALUs, etc. Some kind ofregister transfer language is then often used to describe the decoding and sequencing of each instruction of an ISA using this physical microarchitecture.There are two basic ways to build acontrol unit to implement this description (although many designs use middle ways or compromises):

1. Some computer designs "hardwire" the complete instruction set decoding and sequencing (just like the rest of the microarchitecture).
2. Other designs employmicrocode routines or tables (or both) to do this, usingROMs or writableRAMs (writable control store),PLAs, or both.

Some microcoded CPU designs with a writable control store use it to allow the instruction set to be changed (for example, theRekursiv processor and theImsysCjip).^[20]

CPUs designed forreconfigurable computing may usefield-programmable gate arrays (FPGAs).

An ISA can also beemulated in software by aninterpreter. Naturally, due to the interpretation overhead, this is slower than directly running programs on the emulated hardware, unless the hardware running the emulator is an order of magnitude faster. Today, it is common practice for vendors of new ISAs or microarchitectures to make software emulators available to software developers before the hardware implementation is ready.

Often the details of the implementation have a strong influence on the particular instructions selected for the instruction set. For example, many implementations of theinstruction pipeline only allow a single memory load or memory store per instruction, leading to aload–store architecture (RISC). For another example, some early ways of implementing theinstruction pipeline led to adelay slot.

The demands of high-speed digital signal processing have pushed in the opposite direction—forcing instructions to be implemented in a particular way. For example, to perform digital filters fast enough, the MAC instruction in a typicaldigital signal processor (DSP) must use a kind ofHarvard architecture that can fetch an instruction and two data words simultaneously, and it requires a single-cyclemultiply–accumulatemultiplier.

• Comparison of instruction set architectures
• Compressed instruction set
• Computer architecture
• Emulator
• Instruction set simulator
• Micro-operation
• No instruction set computing
• OVPsim – full systems simulator providing ability to create/model/emulate any instruction set using C and standard APIs
• Processor design
• Simulation
• Register transfer language (RTL)

• Bowen, Jonathan P. (July–August 1985). "Standard Microprocessor Programming Cards".Microprocessors and Microsystems.9 (6):274–290.doi:10.1016/0141-9331(85)90116-4.
• Hennessy, John L.;Patterson, David A. (2003).Computer Architecture: A Quantitative Approach (Third ed.).Morgan Kaufmann Publishers.ISBN 1-55860-724-2. Retrieved2023-03-04.

•   Media related toInstruction set architectures at Wikimedia Commons
• Programming Textfiles: Bowen's Instruction Summary Cards
• Mark Smotherman's Historical Computer Designs Page