| General information | |
|---|---|
| Launched | 2019 |
| Designed by | IBM |
| Performance | |
| Max.CPUclock rate | 5.2[1] GHz |
| Physical specifications | |
| Cores |
|
| Cache | |
| L1cache | 128 KB instruction 128 KB data per core |
| L2 cache | 4 MB instruction 4 MB data per core |
| L3 cache | 256 MB shared |
| Architecture and classification | |
| Technology node | 14 nm[1] |
| Instruction set | z/Architecture |
| History | |
| Predecessor | z14 |
| Successor | Telum |
Thez15 is amicroprocessor made byIBM for theirz15mainframe computers, announced on September 12, 2019.[2]
The processor unit chip (PU chip) has 12 cores. The z15 cores support two-waysimultaneous multithreading.[3]
The cores implement theCISCz/Architecture with asuperscalar,out-of-orderpipeline. New in z15 is an on-chip nest accelerator unit, shared by all cores, to acceleratecompression.[3]
The cache (e.g. level 3) is doubled from the previous generation z14, while the "L4 cache increased from 672MB to 960MB, or +43%" with the new add-on chip system controller (SC) SCM. Both it and all levels of cache in the main processor from level 1 useeDRAM, instead of the traditionally usedSRAM. "A five-CPC drawer system has 4800 MB (5 x 960 MB) of shared L4 cache."[citation needed]