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Wikipedia

I²S

Not to be confused withI²C.
"i2s" redirects here and is not to be confused withIIS (disambiguation),IS2 (disambiguation), orI2 (disambiguation).

Inter-Integrated Circuit Sound (I²S, pronounced "eye-squared-ess"[citation needed]) is aserial interface protocol for transmitting two-channel, digital audio aspulse-code modulation (PCM) betweenintegrated circuit (IC) components of an electronic device. An I²S bus separates clock and serial data signals, resulting in simpler receivers than those required for asynchronous communications systems that need to recover the clock from the data stream. Alternatively, I²S is spelledI2S (pronounced eye-two-ess) orIIS (pronounced eye-eye-ess). Despite a similar name, I²S is unrelated toI²C.

I²S bus
TypeSerial communicationbus
Production history
DesignerPhilips Semiconductor, known today asNXP Semiconductors
Designed1986; 39 years ago (1986)
Data
Data signalPush-pull
Width1 data line (SD) +
2 clock lines (SCK, WS)
ProtocolSerial

History

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The protocol standard was introduced in 1986 by Philips Semiconductor (nowNXP Semiconductors) and was first revised June 5, 1996.[1] The standard was last revised on February 17, 2022 and updated termsmaster andslave tocontroller andtarget.[2]

Details

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Timing diagram of I²S

As shown in the diagram, the protocol requires the following lines:

  • Serial clock (SCK),[1] a.k.a. bit clock (BCLK).[3]
  • Word select (WS);[1] a.k.a. left-right clock (LRCLK)[3] or frame sync (FS).[4] 0 = Left channel, 1 = Right channel[1]
  • Serial data (SD),[1] a.k.a. SDATA, SDIN, SDOUT, DACDAT, ADCDAT[3]

The protocol may also include the following lines:

  • Master clock (typically 256 x LRCLK); not part of the standard,[5] but is commonly included for synchronizing the internal operation of the analog/digital converters[4][6]
  • A multiplexed data line for upload

The bit clock pulses once for each discrete bit of data on the data lines. The bit clock frequency is the product of thesample rate, the number of bits per channel and the number of channels. So, for example, CD Audio with a sample frequency of 44.1 kHz, with 16 bits of precision and two channels (stereo) has a bit clock frequency of:

44.1 kHz × 16 × 2 = 1.4112 MHz

The word select clock lets the device know whether channel 1 (WS = 0) or channel 2 (WS = 1) is currently being sent, because I²S allows two channels to be sent on the same data line. It is a 50% duty-cycle signal that has the same frequency as the sample frequency. For stereo material, the I²S specification states that left audio is transmitted on the low cycle of the word select clock and the right channel is transmitted on the high cycle. It is typically synchronized to the falling edge of the serial clock, as the data is latched on the rising edge.[1] The word select clock changes one bit clock period before the MSB is transmitted. This enables, for example, the receiver to store the previous word and clear the input for the next.[1]

Data issigned, encoded astwo's complement with the MSB (most significant bit)first.[1] This allows the number of bits per frame to be arbitrary, with no negotiation required between transmitter and receiver.[1]

As an audio interconnect

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This sectionneeds additional citations forverification. Relevant discussion may be found on thetalk page. Please helpimprove this article byadding citations to reliable sources in this section. Unsourced material may be challenged and removed.(October 2022) (Learn how and when to remove this message)

In audio equipment, I²S is sometimes used as an external link between a CD player or digital audio streaming device and an externaldigital-to-analog converter, as opposed to a purely internal connection within one player box. This may form an alternative to the commonly usedAES/EBU,Toslink orS/PDIF standards.

The I²S connection was not intended to be used via cables, and most integrated circuits will not have the correct impedance for coaxial cables. As the impedance adaptation error associated with the different line lengths can cause differences in propagation delay between the clock line and data line, this can result in synchronization problems between the SCK, WS and data signals, mainly at high sampling frequencies and bitrates. As the I²S bus doesn't have any error detection mechanism, this can cause significant decoding errors.

There is no standard interconnecting cable for this application. Some manufacturers simply provide threeBNC connectors, an8P8C ("RJ45") socket or aDE-9 connector. Others likeAudio Alchemy (now defunct) usedDIN connectors.PS Audio, Musica Pristina and Wyred4Sound use an HDMI connector.[7] Dutch manufacturer Van Medevoort has implemented Q-link in some of its equipment, which transfers I²S over 4 RCA connectors (data, MCK, LRCK, BCK).

See also

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References

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  1. ^abcdefghi"I²S Specification"(PDF). Philips Semiconductors. June 5, 1996. Archived fromthe original(PDF) on January 2, 2007.
  2. ^"UM11732 I2S bus specification"(PDF). NXP. Retrieved19 March 2022.
  3. ^abcLewis, Jerad (January 2012)."Technical Article MS-2275: Common Inter-IC Digital Interfaces for Audio Data Transfer"(PDF). Analog Devices, Inc.
  4. ^ab"MCLK in I2S audio protocol".electronics.stackexchange.com. Retrieved2016-11-04.Clock source for the delta-sigma modulators and digital filters. ... It is the clock that is used by the audio codec ... to time and/or drive its own internal operation.
  5. ^"PCM1781 (or any I2S DAC) clock sources - Audio Converters Forum - Audio Converters - TI E2E Community".e2e.ti.com. Retrieved2016-11-04.True, the master (modulator) clock is not part of the I2S standard
  6. ^Arbona, Jorge (September 2010)."Application Report SLAA469 Audio Serial Interface Configurations for Audio Codecs"(PDF).Audio converters based on the delta-sigma (ΔΣ) architecture require an internal master clock that operates at a much faster rate than the target sample rate.
  7. ^McGowan, Paul (2010-04-02)."I2S standards from PS Audio".diyAudio. Retrieved2022-09-11.

External links

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