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Incomputer engineering, ahardware description language (HDL) is a specializedcomputer language used to describe the structure and behavior ofelectronic circuits, usually to designapplication-specific integrated circuits (ASICs) and to programfield-programmable gate arrays (FPGAs).
A hardware description language enables a precise,formal description of an electronic circuit that allows for the automated analysis andsimulation of the circuit. It also allows for thesynthesis of an HDL description into anetlist (a specification of physical electronic components and how they are connected together), which can then beplaced and routed to produce theset of masks used to create anintegrated circuit.
A hardware description language looks much like aprogramming language such asC orALGOL; it is a textual description consisting of expressions, statements and control structures. One important difference between most programming languages and HDLs is that HDLs explicitly include the notion of time.
HDLs form an integral part ofelectronic design automation (EDA) systems, especially for complex circuits, such asapplication-specific integrated circuits,microprocessors, andprogrammable logic devices.
Due to the exploding complexity of digital electronic circuits since the 1970s (seeMoore's law), circuit designers neededdigital logic descriptions to be performed at a high level without being tied to a specific electronic technology, such asECL,TTL orCMOS. HDLs were created to implementregister-transfer level abstraction, a model of the data flow and timing of a circuit.[1]
There are two major hardware description languages:VHDL andVerilog. There are different types of description in them: "dataflow, behavioral and structural".Example of dataflow of VHDL:
LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYnot1ISPORT(a:INSTD_LOGIC;b:OUTSTD_LOGIC);ENDnot1;ARCHITECTUREbehavioralOFnot1ISBEGINb<=NOTa;ENDbehavioral;
HDLs are standard text-based expressions of the structure of electronic systems and their behaviour over time. Likeconcurrent programming languages, HDL syntax and semantics include explicit notations for expressingconcurrency. However, in contrast to most softwareprogramming languages, HDLs also include an explicit notion of time, which is a primary attribute of hardware. Languages whose only characteristic is to express circuit connectivity between a hierarchy of blocks are properly classified asnetlist languages used in electriccomputer-aided design. HDL can be used to express designs in structural, behavioral or register-transfer-level architectures for the same circuit functionality; in the latter two cases thesynthesizer decides the architecture and logic gate layout.
HDLs are used to write executable specifications for hardware. A program designed to implement the underlying semantics of the language statements and simulate the progress of time provides the hardware designer with the ability to model a piece of hardware before it is created physically. It is this executability that gives HDLs the illusion of beingprogramming languages, when they are more precisely classified asspecification languages ormodeling languages. Simulators capable of supporting discrete-event (digital) and continuous-time (analog) modeling exist, and HDLs targeted for each are available.
It is certainly possible to represent hardware semantics using traditional programming languages such asC++, which operate oncontrol flow semantics as opposed todata flow, although to function as such, programs must be augmented with extensive and unwieldyclass libraries. Generally, however, software programming languages do not include any capability for explicitly expressing time, and thus cannot function as hardware description languages. Before the introduction ofSystem Verilog in 2002,C++ integration with alogic simulator was one of the few ways to useobject-oriented programming in hardware verification. System Verilog is the first major HDL to offer object orientation and garbage collection.
Using the proper subset of hardware description language, a program called a synthesizer, orlogic synthesis tool, can infer hardware logic operations from the language statements and produce an equivalent netlist of generic hardware primitives[jargon] to implement the specified behaviour.[citation needed] Synthesizers generally ignore the expression of any timing constructs in the text. Digital logic synthesizers, for example, generally useclock edges as the way to time the circuit, ignoring any timing constructs. The ability to have a synthesizable subset of the language does not itself make a hardware description language.
The first hardware description languages appeared in the late 1960s, looking like more traditional languages.[2] The first that had a lasting effect was described in 1971 inC. Gordon Bell and Allen Newell's textComputer Structures.[3] This text introduced the concept ofregister transfer level, first used in the ISP language to describe the behavior of theDigital Equipment Corporation (DEC)PDP-8.[4]
The language became more widespread with the introduction of DEC's PDP-16 RT-Level Modules (RTMs) and a book describing their use.[5]At least two implementations of the basic ISP language (ISPL and ISPS) followed.[6][7]ISPS was well suited to describe relations between theinputs and the outputs of the design and was quickly adopted by commercial teams at DEC, and by several research teams in the US and among its allies in the North Atlantic Treaty Organization (NATO).
The RTM products never succeeded commercially and DEC stopped marketing them in the mid-1980s, as new methods grew more popular, more sovery-large-scale integration (VLSI).
Separate work done about 1979 at theUniversity of Kaiserslautern produced a language called KARL ("KAiserslautern Register Transfer Language"), which included design calculus language features supporting VLSI chip floorplanning[jargon] and structured hardware design. This work was also the basis of KARL's interactive graphic sister language ABL, whose name was aninitialism for "a block diagram language".[8] ABL was implemented in the early 1980s by the Centro Studi e Laboratori Telecomunicazioni (CSELT) in Torino, Italy, producing the ABLED graphic VLSI design editor. In the mid-1980s, a VLSI design framework was implemented around KARL and ABL by an international consortium funded by the Commission of the European Union.[9]
By the late 1970s, design usingprogrammable logic devices (PLDs) became popular, although these designs were primarily limited to designingfinite-state machines. The work atData General in 1980 used these same devices to design theData General Eclipse MV/8000, and commercial need began to grow for a language that could map well to them. By 1983Data I/O introduced ABEL to fill that need.
In 1985, as design shifted to VLSI,Gateway Design Automation introducedVerilog, andIntermetrics released the first completed version of the VHSIC Hardware Description Language (VHDL). VHDL was developed at the behest of theUnited States Department of Defense'sVery High Speed Integrated Circuit Program (VHSIC), and was based on theAda programming language, and on the experience gained with the earlier development of ISPS.[10] Initially, Verilog and VHDL were used to document and simulate circuit designs already captured and described in another form (such asschematic files). HDL simulation enabled engineers to work at a higher level of abstraction than simulation at the schematic level, and thus increased design capacity from hundreds of transistors to thousands.[citation needed] In 1986, with the support of the U.S Department of Defense,VHDL was sponsored as anIEEE standard (IEEE Std 1076), and the first IEEE-standardized version of VHDL, IEEE Std 1076-1987, was approved in December 1987.Cadence Design Systems later acquired Gateway Design Automation for the rights to Verilog-XL, the HDL simulator that would become the de facto standard ofVerilog simulators for the next decade.
The introduction oflogic synthesis for HDLs pushed HDLs from the background into the foreground of digital design. Synthesis tools compiled HDLsource files (written in a constrained format called RTL) into a manufacturable netlist description in terms ofgates andtransistors. Writing synthesizable RTL files required practice and discipline on the part of the designer; compared to a traditional schematic layout, synthesized RTL netlists were almost always larger in area and slower in performance[citation needed]. A circuit design from a skilled engineer, using labor-intensive schematic-capture/hand-layout, would almost always outperform its logically-synthesized equivalent, but the productivity advantage held by synthesis soon displaced digital schematic capture to exactly those areas that were problematic for RTL synthesis: extremely high-speed, low-power, or asynchronous circuitry.
Within a few years, VHDL and Verilog emerged as the dominant HDLs in the electronics industry, while older and less capable HDLs gradually disappeared from use. However, VHDL and Verilog share many of the same limitations, such as being unsuitable for analog ormixed-signal circuit simulation. Specialized HDLs (such as Confluence) were introduced with the explicit goal of fixing specific limitations of Verilog and VHDL, though none were ever intended to replace them.
Over the years, much effort has been invested in improving HDLs. The latest iteration of Verilog, formally known as IEEE 1800-2005 SystemVerilog, introduces many new features (classes, random variables, and properties/assertions) to address the growing need for bettertest bench randomization, design hierarchy, and reuse. A future revision of VHDL is also in development[when?], and is expected to match SystemVerilog's improvements.
As a result of the efficiency gains realized using HDL, a majority of modern digital circuit design revolves around it. Most designs begin as a set of requirements or a high-level architectural diagram. Control and decision structures are often prototyped inflowchart applications, or entered in a editor. The process of writing the HDL description is highly dependent on the nature of the circuit and the designer's preference for coding style. The HDL is merely the 'capture language', often beginning with a high-level algorithmic description such as a C++ mathematical model. Designers often use scripting languages such asPerl to automatically generate repetitive circuit structures in the HDL language. Special text editors offer features for automatic indentation, syntax-dependent coloration, andmacro-based expansion of the entity/architecture/signal declaration.
The HDL code then undergoes a code review, or auditing. In preparation for synthesis, the HDL description is subject to an array of automated checkers. The checkers report deviations from standardized code guidelines, identify potential ambiguous code constructs before they can cause misinterpretation, and check for common logical coding errors, such as floatingports orshorted outputs. This process aids in resolving errors before the code is synthesized.
In industry parlance, HDL design generally ends at the synthesis stage. Once the synthesis tool has mapped the HDL description into a gate netlist, the netlist is passed off to the back-end stage. Depending on the physical technology (FPGA,ASICgate array, ASICstandard cell), HDLs may or may not play a significant role in the back-end flow. In general, as the design flow progresses toward a physically realizable form, the design database becomes progressively more laden with technology-specific information, which cannot be stored in a generic HDL description. Finally, an integrated circuit is manufactured or programmed for use.
Essential to HDL design is the ability to simulate HDL programs. Simulation allows an HDL description of a design (called a model) to passdesign verification, an important milestone that validates the design's intended function (specification) against the code implementation in the HDL description. It also permits architectural exploration. The engineer can experiment with design choices by writing multiple variations of a base design, then comparing their behavior in simulation. Thus, simulation is critical for successful HDL design.
To simulate an HDL model, an engineer writes a top-level simulation environment (called atest bench). At minimum, a testbench contains an instantiation of the model (called the device under test or DUT), pin/signal declarations for the model's I/O, and a clock waveform. The testbench code is event driven: the engineer writes HDL statements to implement the (testbench-generated) reset-signal, to model interface transactions (such as a host–bus read/write), and to monitor the DUT's output. An HDL simulator — the program that executes the testbench — maintains the simulator clock, which is the master reference for all events in the testbench simulation. Events occur only at the instants dictated by the testbench HDL (such as a reset-toggle coded into the testbench), or in reaction (by the model) to stimulus and triggering events. Modern HDL simulators have full-featuredgraphical user interfaces, complete with a suite of debug tools. These allow the user to stop and restart the simulation at any time, insert simulator breakpoints (independent of the HDL code), and monitor or modify any element in the HDL model hierarchy. Modern simulators can also link the HDL environment to user-compiled libraries, through a definedPLI/VHPI interface. Linking is system-dependent (x86,SPARC etc. runningWindows/Linux/Solaris), as the HDL simulator and user libraries are compiled and linked outside the HDL environment.
Design verification is often the most time-consuming portion of the design process, due to the disconnect between a device'sfunctional specification, the designer's interpretation of the specification, and the imprecision[citation needed] of the HDL language. The majority of the initial test/debug cycle is conducted in the HDLsimulator environment, as the early stage of the design is subject to frequent and major circuit changes. An HDL description can also be prototyped and tested in hardware —programmable logic devices are often used for this purpose. Hardware prototyping is comparatively more expensive than HDL simulation, but offers a real-world view of the design. Prototyping is the best way to check interfacing against other hardware devices and hardware prototypes. Even those running on slow FPGAs offer much shorter simulation times than pure HDL simulation.
Historically, design verification was a laborious, repetitive loop of writing and running simulationtest cases against the design under test. As chip designs have grown larger and more complex, the task of design verification has grown to the point where it now dominates the schedule of a design team. Looking for ways to improve design productivity, theelectronic design automation industry developed theProperty Specification Language.
Informal verification terms, a property is a factual statement about the expected or assumed behavior of another object. Ideally, for a given HDL description, a property or properties can be proven true or false using formal mathematical methods. In practical terms, many properties cannot be proven because they occupy an unboundedsolution space. However, if provided a set of operating assumptions or constraints, a property checker can prove (or disprove) certain properties by narrowing the solution space.
The assertions do not model circuit activity, but capture and document the designer's intent in the HDL code. In a simulation environment, the simulator evaluates all specified assertions, reporting the location and severity of any violations. In a synthesis environment, the synthesis tool usually operates with the policy of halting synthesis upon any violation. Assertion based verification is still in its infancy, but is expected to become an integral part of the HDL design toolset.
An HDL is grossly similar to a softwareprogramming language, but there are major differences. Most programming languages are inherentlyprocedural (single-threaded), with limited syntactical and semantic support to handleconcurrency. HDLs, on the other hand, resembleconcurrent programming languages in their ability to model multiple parallel processes (such asflip-flops andadders) that automatically execute independently of one another. Any change to the process's input automatically triggers an update in the simulator's process stack.
Both programming languages and HDLs are processed by a compiler (often called a synthesizer in the HDL case), but with different goals. For HDLs, "compiling" refers tologic synthesis; the process of transforming the HDL code listing into a physically realizable gatenetlist. The netlist output can take any of many forms: a "simulation" netlist with gate-delay information, a "handoff" netlist for post-synthesisplacement and routing on a semiconductor die, or a generic industry-standardElectronic Design Interchange Format (EDIF) (for subsequent conversion to aJEDEC-format file).
On the other hand, a software compiler converts the source-code listing into amicroprocessor-specific object code for execution on the target microprocessor. As HDLs and programming languages borrow concepts and features from each other, the boundary between them is becoming less distinct. However, pure HDLs are unsuitable for general purposeapplication software development,[why?] just asgeneral-purpose programming languages are undesirable for modeling hardware.
Yet as electronic systems grow increasingly complex, andreconfigurable systems become increasingly common, there is growing desire in the industry for a single language that can perform some tasks of both hardware design and software programming.SystemC is an example of such—embedded system hardware can be modeled as non-detailed architectural blocks (black boxes with modeled signal inputs and output drivers). The target application is written in C or C++ and natively compiled for the host-development system; as opposed to targeting the embedded CPU, which requires host-simulation of the embedded CPU or an emulated CPU.
The high level of abstraction of SystemC models is well suited to earlyarchitecture exploration, as architectural modifications can be easily evaluated with little concern for signal-level implementation issues. However, the threading model used in SystemC relies onshared memory, causing the language not to handle parallel execution or low-level models well.
In their level of abstraction, HDLs have been compared toassembly languages.[citation needed] There are attempts to raise the abstraction level of hardware design in order to reduce the complexity of programming in HDLs, creating a sub-field calledhigh-level synthesis.
Companies such asCadence,Synopsys and Agility Design Solutions are promotingSystemC as a way to combine high-level languages with concurrency models to allow faster design cycles forFPGAs than is possible using traditional HDLs. Approaches based on standardC orC++ (with libraries or other extensions allowing parallel programming) are found in theCatapult C tools fromMentor Graphics, and theImpulse C tools from Impulse Accelerated Technologies.
A similar initiative from Intel is the use of Data Parallel C++, related toSYCL, as a high-level synthesis language.
Annapolis Micro Systems, Inc.'s CoreFire Design Suite[11] andNational Instruments LabVIEW FPGA provide a graphicaldataflow approach to high-level design entry and languages such asSystemVerilog, SystemVHDL, andHandel-C seek to accomplish the same goal, but are aimed at making existing hardware engineers more productive, rather than making FPGAs more accessible to existingsoftware engineers.
It is also possible to design hardware modules usingMATLAB andSimulink using theMathWorks HDL Coder tool[12] or DSP Builder for Intel FPGAs[13] or Xilinx System Generator (XSG) fromXilinx.[14]
| Name | Description |
|---|---|
| HDL-A | A proprietary analog HDL |
| SpectreHDL | A proprietary analog HDL fromCadence Design Systems for its Spectre circuit simulator |
| Verilog-AMS (Verilog for Analog and Mixed-Signal) | AnAccellera standard extension of IEEE Std 1364Verilog for analog and mixed-signal simulation |
| VHDL-AMS (VHDL with Analog/Mixed-Signal extension) | AnIEEE standard extension (IEEE Std 1076.1) ofVHDL for analog and mixed-signal simulation |
The two most widely used and well-supported HDL varieties used in industry areVerilog andVHDL.
| Status | Name | Hostlanguage | Description |
|---|---|---|---|
| In use | Altera Hardware Description Language (AHDL) | Proprietary language fromAltera | |
| A Hardware Programming language (AHPL) | Used as a tool for teaching | ||
| Amaranth | Python | ||
| Bluespec | High-level HDL based onHaskell (not embeddedDSL)[15] | ||
| BluespecSystemVerilog (BSV) | Based onBluespec, withVerilog HDL like syntax, by Bluespec, Inc. | ||
| C-to-Verilog | Converter from C to Verilog | ||
| Chisel (Constructing Hardware in a Scala Embedded Language)[16] | Scala | Based onScala (embeddedDSL) | |
| Clash | Functional hardware description language that borrows its syntax and semantics from the functional languageHaskell | ||
| Common Oriented Language for Architecture of Multi Objects (COLAMO)[17][18] | Proprietary language from “Supercomputers and Neurocomputers Research Center” Co Ltd. | ||
| Compiler for Universal Programmable Logic (CUPL)[19] | Proprietary language from Logical Devices, Inc. | ||
| DSLX | Domain-specific language for XLS toolchain | ||
| ESys.net | .NET framework written in C# | ||
| Filament | HDL with a type system inspired by Rust | ||
| Handel-C | C-like design language | ||
| Hardcaml | OCaml | Based onOCaml (embedded DSL)[20] | |
| HHDL | Haskell | Based onHaskell (embedded DSL) | |
| HardwareJoin Java (HJJ) | Join Java | Based onJoin Java | |
| Hardware ML (HML) | Standard ML | Based onStandard ML[21] | |
| Hydra | Haskell | Based onHaskell | |
| Impulse C | C-like HDL | ||
| Parallel C++ (ParC) | kusu extended with HDL style threading and communication for task-parallel programming | ||
| JHDL | Java | Just Another Hardware Definition Language based onJava | |
| Lava | Haskell | Based onHaskell (embedded DSL)[22][23][24][25] | |
| Lola | Simple language used for teaching | ||
| M | HDL fromMentor Graphics | ||
| Migen | Python | ||
| MyHDL | Python | Based onPython (embeddedDSL) | |
| PALASM | ForProgrammable Array Logic (PAL) devices | ||
| PipelineC | C-like hardware description language addingHigh-level synthesis-like automatic pipelining as a language construct and compiler feature. | ||
| PyMTL 3 (Mamba) | Python | Based on Python, from Cornell University | |
| PyRTL | Python | Based on Python, from University of California, Santa Barbara | |
| Riverside Optimizing Compiler for Configurable Computing (ROCCC) | Free and open-source C to HDL tool | ||
| RHDL | Ruby | Based on theRuby programming language | |
| Rapid Open Hardware Development (ROHD)[26] | Dart | Framework for hardware design and verification, written inDart | |
| Ruby (hardware description language) | |||
| Silice | HDL that simplifies designing hardware algorithms with parallelism and pipelines | ||
| Spade | HDL inspired by modern software languages like Rust | ||
| SystemC | Standardized class ofC++ libraries for high-level behavioral and transaction modeling ofdigital hardware at a high level of abstraction, i.e., system-level | ||
| SystemVerilog | Superset of Verilog, with enhancements to address system-level design and verification | ||
| SpinalHDL | Scala | Based on Scala (embedded DSL) | |
| SystemTCL | SDL based on Tcl | ||
| Templated HDL inspired by C++ (THDL++) | Extension of VHDL with inheritance, advanced templates and policy classes | ||
| Torii | Python | A Python-based HDL and framework for FPGA and ASIC designs with support for both proprietary and open source EDA tooling. | |
| Verik | Kotlin reinterpreted with the semantics of an HDL; transpiled toSystemVerilog | ||
| Transaction-Level Verilog (TL-Verilog)[27] | Extension of Verilog/SystemVerilog with constructs forpipelines andtransactions. | ||
| Verilog | One of the most widely used and well-supported HDLs | ||
| Veryl | HDL designed as SystemVerilog alternative | ||
| VHDL (VHSIC HDL) | One of the most widely used and well-supported HDLs | ||
| No longer in common use | Advanced Boolean Expression Language (ABEL) | Obsolete HDL made byData I/O Corporation in 1983 | |
| Confluence | Functional HDL, discontinued | ||
| CoWareC | C-based HDL byCoWare; discontinued in favor of SystemC | ||
| ELLA | No longer in common use | ||
| ISPS | Original HDL from CMU; no longer in common use | ||
| KAiserslautern Register Language (KARL)[9] | Pascal-like hardware description language; no longer in common use | ||
| nMigen | Python | Predecessor to Amaranth |
Several projects exist for definingprinted circuit board connectivity using language based, textual-entry methods. Among these, new approaches have emerged that focus on enhancing readability, reusability, and validation. These modern methodologies employ open-source design languages specifically tailored for electronics, adopting declarative markup to specify what circuits should achieve. This shift integrates software development principles into hardware design, streamlining the process and emphasizing automation, reuse, and validation.
| Name | Description |
|---|---|
| atopile | An open-source language and toolchain to describe electronic circuit boards with code. |
| PHDL (PCB HDL) | A free and open source HDL for defining printed circuit board connectivity. |
| EDAsolver | An HDL for solving schematic designs based on constraints. |
| SKiDL | Open source Python module to design electronic circuits. |
| International | |
|---|---|
| National | |
| Other | |
