Hardware acceleration is the use ofcomputer hardware designed to perform specific functions more efficiently when compared tosoftware running on a general-purposecentral processing unit (CPU). Anytransformation ofdata that can be calculated in software running on a generic CPU can also be calculated in custom-made hardware, or in some mix of both.

To perform computing tasks more efficiently, generally one can invest time and money in improving the software, improving the hardware, or both. There are various approaches with advantages and disadvantages in terms of decreasedlatency, increasedthroughput, and reducedenergy consumption. Typical advantages of focusing on software may include greater versatility, more rapiddevelopment, lowernon-recurring engineering costs, heightenedportability, and ease ofupdating features orpatchingbugs, at the cost ofoverhead to compute general operations. Advantages of focusing on hardware may includespeedup, reducedpower consumption,^[1] lower latency, increasedparallelism^[2] andbandwidth, andbetter utilization of area andfunctional components available on anintegrated circuit; at the cost of lower ability to update designs onceetched onto silicon and higher costs offunctional verification, times to market, and the need for more parts. In the hierarchy of digital computing systems ranging from general-purpose processors tofully customized hardware, there is a tradeoff between flexibility and efficiency, with efficiency increasing byorders of magnitude when any given application is implemented higher up that hierarchy.^[3] This hierarchy includes general-purpose processors such as CPUs,^[4] more specialized processors such as programmableshaders in aGPU,^[5] applications implemented onfield-programmable gate arrays (FPGAs),^[6] and fixed-function implemented onapplication-specific integrated circuits (ASICs).^[7]

Hardware acceleration is advantageous forperformance, and practical when the functions are fixed, so updates are not as needed as in software solutions. With the advent ofreprogrammablelogic devices such as FPGAs, the restriction of hardware acceleration to fully fixed algorithms has eased since 2010, allowing hardware acceleration to be applied to problem domains requiring modification to algorithms and processingcontrol flow.^[8][9] The disadvantage, however, is that in many open source projects, it requires proprietary libraries that not all vendors are keen to distribute or expose, making it difficult to integrate in such projects.

Integrated circuits are designed to handle various operations on both analog and digital signals. In computing, digital signals are the most common and are typically represented as binary numbers.Computer hardware and software use thisbinary representation to perform computations. This is done by processingBoolean functions on the binary input, and then outputting the results for storage or further processing by other devices.

Because allTuring machines can run anycomputable function, it is always possible to design custom hardware that performs the same function as a given piece of software. Conversely, software can always be used to emulate the function of a given piece of hardware. Custom hardware may offer higher performance per watt for the same functions that can be specified in software.Hardware description languages (HDLs) such asVerilog andVHDL can model the samesemantics as software andsynthesize the design into anetlist that can be programmed to an FPGA or composed into thelogic gates of an ASIC.

The vast majority of software-based computing occurs on machines implementing thevon Neumann architecture, collectively known asstored-program computers.Computer programs are stored as data andexecuted byprocessors. Such processors must fetch and decode instructions, as well asload data operands frommemory (as part of theinstruction cycle), to execute the instructions constituting the software program. Relying on a commoncache for code and data leads to the "von Neumann bottleneck", a fundamental limitation on the throughput of software on processors implementing the von Neumann architecture. Even in themodified Harvard architecture, where instructions and data have separate caches in thememory hierarchy, there is overhead to decoding instructionopcodes andmultiplexing availableexecution units on amicroprocessor ormicrocontroller, leading to low circuit utilization. Modern processors that providesimultaneous multithreading exploit under-utilization of available processor functional units andinstruction level parallelism between different hardware threads.

Hardware execution units do not in general rely on the von Neumann or modified Harvard architectures and do not need to perform the instruction fetch and decode steps of aninstruction cycle and incur those stages' overhead. If needed calculations are specified in aregister transfer level (RTL) hardware design, the time and circuit area costs that would be incurred by instruction fetch and decoding stages can be reclaimed and put to other uses.

This reclamation saves time, power, and circuit area in computation. The reclaimed resources can be used for increased parallel computation, other functions, communication, or memory, as well as increasedinput/output capabilities. This comes at the cost of general-purpose utility.

Greater RTL customization of hardware designs allows emerging architectures such asin-memory computing,transport triggered architectures (TTA) andnetworks-on-chip (NoC) to further benefit from increasedlocality of data to execution context, thereby reducing computing and communication latency between modules and functional units.

Custom hardware is limited in parallel processing capability only by the area andlogic blocks available on theintegrated circuit die.^[10] Therefore, hardware is much more free to offermassive parallelism than software on general-purpose processors, offering a possibility of implementing theparallel random-access machine (PRAM) model.

It is common to buildmulticore andmanycore processing units out ofmicroprocessor IP core schematics on a single FPGA or ASIC.^{[11][12][13][14][15]} Similarly, specialized functional units can be composed in parallel, asin digital signal processing, without being embedded in a processorIP core. Therefore, hardware acceleration is often employed for repetitive, fixed tasks involving littleconditional branching, especially on large amounts of data. This is howNvidia'sCUDA line of GPUs are implemented.

As device mobility has increased, new metrics have been developed that measure the relative performance of specific acceleration protocols, considering characteristics such as physical hardware dimensions, power consumption, and operations throughput. These can be summarized into three categories: task efficiency, implementation efficiency, and flexibility. Appropriate metrics consider the area of the hardware along with both the corresponding operations throughput and energy consumed.^[16]

Examples of hardware acceleration includebit blit acceleration functionality in graphics processing units (GPUs), use ofmemristors for acceleratingneural networks, andregular expression hardware acceleration forspam control in theserver industry, intended to preventregular expression denial of service (ReDoS) attacks.^[17] The hardware that performs the acceleration may be part of a general-purpose CPU, or a separate unit called a hardware accelerator, though they are usually referred to with a more specific term, such as 3D accelerator, orcryptographic accelerator.

Traditionally, processors were sequential (instructions are executed one by one), and were designed to run general purpose algorithms controlled byinstruction fetch (for example, moving temporary resultsto and from aregister file). Hardware accelerators improve the execution of a specific algorithm by allowing greaterconcurrency, having specificdatapaths for theirtemporary variables, and reducing the overhead of instruction control in the fetch-decode-execute cycle.

Modern processors aremulti-core and often feature parallel "single-instruction; multiple data" (SIMD) units. Even so, hardware acceleration still yields benefits. Hardware acceleration is suitable for any computation-intensive algorithm which is executed frequently in a task or program. Depending upon the granularity, hardware acceleration can vary from a small functional unit, to a large functional block (likemotion estimation inMPEG-2).

• Coprocessor
• DirectX Video Acceleration (DXVA)
• Direct memory access (DMA)
• High-level synthesis
  • C to HDL
  • Flow to HDL
• Soft microprocessor
• Flynn's taxonomy of parallelcomputer architectures
  • Single instruction, multiple data (SIMD)
  • Single instruction, multiple threads (SIMT)
  • Multiple instructions, multiple data (MIMD)
• Computer for operations with functions

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