 Broadcom BCM2712, asystem on a chip with four ARM Cortex-A76 CPUs | |
| General information | |
|---|---|
| Launched | 2018[1] |
| Designed by | ARM Holdings |
| Performance | |
| Max.CPUclock rate | to 3 GHz in phones, 3.3 GHz in tablets/laptops |
| Address width | 40-bit |
| Physical specifications | |
| Cores |
|
| Co-processor | ARM Cortex-A55 (optional) |
| Cache | |
| L1cache | 128KiB (64 KiBD-cache and64 KiBI-cache with parity) per core |
| L2 cache | 128–512 KiB per core |
| L3 cache | 512 KiB–4 MiB (optional) |
| Architecture and classification | |
| Technology node | 7 nm |
| Instruction set | ARMv8-A:A64,A32, T32 |
| Extensions | |
| Products, models, variants | |
| Product code name |
|
| Variant | |
| History | |
| Predecessors | ARM Cortex-A75 ARM Cortex-A73 ARM Cortex-A72 |
| Successor | ARM Cortex-A77 |
TheARM Cortex-A76 is acentral processing unit (CPU) core implementing the 64-bitARMv8.2-A architecture, designed byArm Holdings' design center inAustin, Texas. Compared to its predecessor, theCortex-A75, ARM claimed performance improvements of up to 25% in integer operations and 35% in floating-point operations.[2]
The Cortex-A76 is a successor to both theCortex-A73 andCortex-A75, though it is based on an entirely new microarchitecture. It features a 4-wide decode, out-of-order, superscalar pipeline. The frontend can fetch and decode four instructions per cycle and dispatch up to four macro-operations and eight micro-operations per cycle. The out-of-order execution window includes 128 entries. The backend includes eight execution ports, with a pipeline depth of 13 stages and execution latencies of 11 stages.[2][3]
The Cortex-A76 supports unprivileged 32-bit applications, but privileged software, such as operating systems and kernels, must use the 64-bitARMv8-A instruction set.[4] Additional features include support for ARMv8.3-A's LDAPR instructions, ARMv8.4-A's dot product instructions, and ARMv8.5-A's speculative execution controls such as SSBS, CSDB, SSBB, and PSSBB.[5]
Memory bandwidth is improved by up to 90% over the Cortex-A75.[6][7] ARM targeted the Cortex-A76 for high-performance computing, includingWindows 10 laptops,[8] positioning it as a competitor toIntel’sKaby Lake architecture.[9]
The Cortex-A76 also supportsARM DynamIQ technology, and is often paired with energy-efficientCortex-A55 cores in multi-core configurations.[2]
The Cortex-A76 is available as asemiconductor intellectual property core (SIP core) and can be licensed by manufacturers for integration into customsystem on a chip (SoC) designs. It is commonly combined with other components such asgraphics processing units (GPUs),digital signal processors (DSPs), andimage signal processors (ISPs) on a single chip.
The Cortex-A76 first appeared in theHiSilicon Kirin 980 SoC.[10] The company's later Kirin 985 and 990 series of SoCs would also use the A76.
ARM collaborated withQualcomm on semi-custom versions of the Cortex-A76 used in several of itsKryo CPU designs, including the Kryo 495 (Snapdragon 8cx), Kryo 485 (Snapdragon 855/855 Plus), Kryo 470 (Snapdragon 730), and Kryo 460 (Snapdragon 675). Qualcomm made several architectural modifications, such as increasing the reorder buffer to expand the out-of-order execution window.[11]
Other SoCs using the Cortex-A76 include: