90 nm process

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The90 nm process refers to the technology used insemiconductor manufacturing to createintegrated circuits with a minimum feature size of 90 nanometers. It was an advancement over the previous130 nm process. Eventually, it was succeeded by smaller process nodes, such as the65 nm,45 nm, and32 nm processes.

It was commercialized by the 2003–2005 timeframe, by semiconductor companies includingToshiba,Sony,Samsung,IBM,Intel,Fujitsu,TSMC,Elpida,AMD,Infineon,Texas Instruments andMicron Technology.

The origin of the 90 nm value is historical; it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by theInternational Technology Roadmap for Semiconductors (ITRS).

The 300 mm wafer size became mainstream at the 90 nm node. The previous wafer size was 200 mm diameter.

The 193 nm wavelength was introduced by many (but not all) companies forlithography of critical layers mainly during the 90 nm node. Yield issues associated with this transition (due to the use of newphotoresists) were reflected in the high costs associated with this transition.

Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit;^[1] neither gate length, metal pitch or gate pitch on a "90nm" device is ninety nanometers.^[2]^[3]^[4]^[5]

History

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A 90 nmsilicon MOSFET wasfabricated by Iranian engineerGhavam Shahidi (laterIBM director) with D.A. Antoniadis and H.I. Smith atMIT in 1988. The device was fabricated usingX-ray lithography.^[6]

Toshiba, Sony and Samsung developed a 90 nm process during 2001–2002, before being introduced in 2002 for Toshiba'seDRAM and Samsung's 2 Gb NAND flash memory.^[7]^[8] IBM demonstrated a 90 nmsilicon-on-insulator (SOI)CMOS process, with development led by Shahidi, in 2002. The same year, Intel demonstrated a 90 nmstrained-silicon process.^[9] Fujitsu commercially introduced its 90 nm process in 2003^[10] followed by TSMC in 2004.^[11]

Gurtej Singh Sandhu of Micron Technology initiated the development ofatomic layer deposition high-kfilms forDRAM memory devices. This helped drive cost-effective implementation ofsemiconductor memory, starting with 90 nmnode DRAM.^[12]

Intel's 90nm process has a transistor density of 1.45 million transistors per square milimeter (MTr/mm2).^[13]