MicroEngine Scheduler (MES)¶
Note
Queue and ring buffer are used as a synonymous.
Note
This section assumes that you are familiar with the concept of Pipes, Queues, and GC.If not, checkGFX, Compute, and SDMA Overall Behavioranddrm/amdgpu - Graphics and Compute (GC).
Every GFX has a pipe component with one or more hardware queues. Pipes canswitch between queues depending on certain conditions, and one of thecomponents that can request a queue switch to a pipe is the MicroEngineScheduler (MES). Whenever the driver is initialized, it creates one MQD perhardware queue, and then the MQDs are handed to the MES firmware for mappingto:
Kernel Queues (legacy): This queue is statically mapped to HQDs and neverpreempted. Even though this is a legacy feature, it is the current default, andmost existing hardware supports it. When an application submits work to thekernel driver, it submits all of the application command buffers to the kernelqueues. The CS IOCTL takes the command buffer from the applications andschedules them on the kernel queue.
User Queues: These queues are dynamically mapped to the HQDs. Regarding theutilization of User Queues, the userspace application will create its userqueues and submit work directly to its user queues with no need to IOCTL foreach submission and no need to share a single kernel queue.
In terms of User Queues, MES can dynamically map them to the HQD. If there aremore MQDs than HQDs, the MES firmware will preempt other user queues to makesure each queues get a time slice; in other words, MES is a microcontrollerthat handles the mapping and unmapping of MQDs into HQDs, as well as thepriorities and oversubscription of MQDs.