Layer¶

Layer is the first pipeline stage, which prepares the pixel data for the nextstage. It fetches the pixel from memory, decodes it if it’s AFBC, rotates thesource image, unpacks or converts YUV pixels to the device internal RGB pixels,then adjusts the color_space of pixels if needed.

Scaler¶

As its name suggests, scaler takes responsibility for scaling, and D71 alsosupports image enhancements by scaler.The usage of scaler is very flexible and can be connected to layer outputfor layer scaling, or connected to compositor and scale the whole displayframe and then feed the output data into wb_layer which will then write itinto memory.

Compositor (compiz)¶

Compositor blends multiple layers or pixel data flows into one single displayframe. its output frame can be fed into post image processor for showing it onthe monitor or fed into wb_layer and written to memory at the same time.user can also insert a scaler between compositor and wb_layer to down scalethe display frame first and then write to memory.

Writeback Layer (wb_layer)¶

Writeback layer does the opposite things of Layer, which connects to compizand writes the composition result to memory.

Post image processor (improc)¶

Post image processor adjusts frame data like gamma and color space to fit therequirements of the monitor.

Timing controller (timing_ctrlr)¶

Final stage of display pipeline, Timing controller is not for the pixelhandling, but only for controlling the display timing.

Merger¶

D71 scaler mostly only has the half horizontal input/output capabilitiescompared with Layer, like if Layer supports 4K input size, the scaler only cansupport 2K input/output in the same time. To achieve the ful frame scaling, D71introduces Layer Split, which splits the whole image to two half parts and feedsthem to two Layers A and B, and does the scaling independently. After scalingthe result need to be fed to merger to merge two part images together, and thenoutput merged result to compiz.

Splitter¶

Similar to Layer Split, but Splitter is used for writeback, which splits thecompiz result to two parts and then feed them to two scalers.

Single pipeline data flow¶

digraph single_ppl {   rankdir=LR;   subgraph {      "Memory";      "Monitor";   }   subgraph cluster_pipeline {       style=dashed       node [shape=box]       {           node [bgcolor=grey style=dashed]           "Scaler-0";           "Scaler-1";           "Scaler-0/1"       }      node [bgcolor=grey style=filled]      "Layer-0" -> "Scaler-0"      "Layer-1" -> "Scaler-0"      "Layer-2" -> "Scaler-1"      "Layer-3" -> "Scaler-1"      "Layer-0" -> "Compiz"      "Layer-1" -> "Compiz"      "Layer-2" -> "Compiz"      "Layer-3" -> "Compiz"      "Scaler-0" -> "Compiz"      "Scaler-1" -> "Compiz"      "Compiz" -> "Scaler-0/1" -> "Wb_layer"      "Compiz" -> "Improc" -> "Timing Controller"   }   "Wb_layer" -> "Memory"   "Timing Controller" -> "Monitor"}

Dual pipeline with Slave enabled¶

digraph slave_ppl {   rankdir=LR;   subgraph {      "Memory";      "Monitor";   }   node [shape=box]   subgraph cluster_pipeline_slave {       style=dashed       label="Slave Pipeline_B"       node [shape=box]       {           node [bgcolor=grey style=dashed]           "Slave.Scaler-0";           "Slave.Scaler-1";       }      node [bgcolor=grey style=filled]      "Slave.Layer-0" -> "Slave.Scaler-0"      "Slave.Layer-1" -> "Slave.Scaler-0"      "Slave.Layer-2" -> "Slave.Scaler-1"      "Slave.Layer-3" -> "Slave.Scaler-1"      "Slave.Layer-0" -> "Slave.Compiz"      "Slave.Layer-1" -> "Slave.Compiz"      "Slave.Layer-2" -> "Slave.Compiz"      "Slave.Layer-3" -> "Slave.Compiz"      "Slave.Scaler-0" -> "Slave.Compiz"      "Slave.Scaler-1" -> "Slave.Compiz"   }   subgraph cluster_pipeline_master {       style=dashed       label="Master Pipeline_A"       node [shape=box]       {           node [bgcolor=grey style=dashed]           "Scaler-0";           "Scaler-1";           "Scaler-0/1"       }      node [bgcolor=grey style=filled]      "Layer-0" -> "Scaler-0"      "Layer-1" -> "Scaler-0"      "Layer-2" -> "Scaler-1"      "Layer-3" -> "Scaler-1"      "Slave.Compiz" -> "Compiz"      "Layer-0" -> "Compiz"      "Layer-1" -> "Compiz"      "Layer-2" -> "Compiz"      "Layer-3" -> "Compiz"      "Scaler-0" -> "Compiz"      "Scaler-1" -> "Compiz"      "Compiz" -> "Scaler-0/1" -> "Wb_layer"      "Compiz" -> "Improc" -> "Timing Controller"   }   "Wb_layer" -> "Memory"   "Timing Controller" -> "Monitor"}

Sub-pipelines for input and output¶

A complete display pipeline can be easily divided into three sub-pipelinesaccording to the in/out usage.

digraph layer_data_flow {   rankdir=LR;   node [shape=box]   {      node [bgcolor=grey style=dashed]        "Scaler-n";   }   "Layer-n" -> "Scaler-n" -> "Compiz"}

digraph layer_data_flow {   rankdir=LR;   node [shape=box]   "Layer-0/1" -> "Scaler-0" -> "Merger"   "Layer-2/3" -> "Scaler-1" -> "Merger"   "Merger" -> "Compiz"}

digraph writeback_data_flow {   rankdir=LR;   node [shape=box]   {      node [bgcolor=grey style=dashed]        "Scaler-n";   }   "Compiz" -> "Scaler-n" -> "Wb_layer"}

digraph writeback_data_flow {   rankdir=LR;   node [shape=box]   "Compiz" -> "Splitter"   "Splitter" -> "Scaler-0" -> "Merger"   "Splitter" -> "Scaler-1" -> "Merger"   "Merger" -> "Wb_layer"}

digraph single_ppl {   rankdir=LR;   node [shape=box]   "Compiz" -> "Improc" -> "Timing Controller"}

struct komeda_pipeline/component¶

To fully utilize and easily access/configure the HW, the driver side also usesa similar architecture: Pipeline/Component to describe the HW features andcapabilities, and a specific component includes two parts:

• Data flow controlling.

• Specific component capabilities and features.

So the driver defines a common headerstructkomeda_component to describe thedata flow control and all specific components are a subclass of this basestructure.

structkomeda_component¶

struct komeda_component {    struct drm_private_obj obj;    struct komeda_pipeline *pipeline;    char name[32];    u32 __iomem *reg;    u32 id;    u32 hw_id;    u8 max_active_inputs;    u8 max_active_outputs;    u32 supported_inputs;    u32 supported_outputs;    const struct komeda_component_funcs *funcs;};

Description

structkomeda_component describe the data flow capabilities for how to link acomponent into the display pipeline.all specified components are subclass of this structure.

structkomeda_component_output¶

struct komeda_component_output {    struct komeda_component *component;    u8 output_port;};

Description

a component has multiple outputs, if want to know where the datacomes from, only know the component is not enough, we still need to knowits output port

structkomeda_component_state¶

struct komeda_component_state {    struct drm_private_state obj;    struct komeda_component *component;    union {        struct drm_crtc *crtc;        struct drm_plane *plane;        struct drm_connector *wb_conn;        void *binding_user;    };    u16 active_inputs;    u16 changed_active_inputs;    u16 affected_inputs;    struct komeda_component_output inputs[KOMEDA_COMPONENT_N_INPUTS];};

Description

component_state is the data flow configuration of the component, and it’sthe superclass of all specific component_state likekomeda_layer_state,komeda_scaler_state

structkomeda_pipeline¶

struct komeda_pipeline {    struct drm_private_obj obj;    struct komeda_dev *mdev;    struct clk *pxlclk;    int id;    u32 avail_comps;    u32 standalone_disabled_comps;    int n_layers;    struct komeda_layer *layers[KOMEDA_PIPELINE_MAX_LAYERS];    int n_scalers;    struct komeda_scaler *scalers[KOMEDA_PIPELINE_MAX_SCALERS];    struct komeda_compiz *compiz;    struct komeda_splitter *splitter;    struct komeda_merger *merger;    struct komeda_layer  *wb_layer;    struct komeda_improc *improc;    struct komeda_timing_ctrlr *ctrlr;    const struct komeda_pipeline_funcs *funcs;    struct device_node *of_node;    struct device_node *of_output_port;    struct device_node *of_output_links[2];    bool dual_link;};

Description

Represent a complete display pipeline and hold all functional components.

structkomeda_pipeline_state¶

struct komeda_pipeline_state {    struct drm_private_state obj;    struct komeda_pipeline *pipe;    struct drm_crtc *crtc;    u32 active_comps;};

NOTE

Unlike the pipeline, pipeline_state doesn’t gather any component_stateinto it. It because all component will be managed by drm_atomic_state.

How to map plane to Layer(input) pipeline¶

Komeda has multiple Layer input pipelines, see:-Single pipeline data flow-Dual pipeline with Slave enabled

The easiest way is binding a plane to a fixed Layer pipeline, but consider thekomeda capabilities:

• Layer Split, SeeLayer(input) pipeline

  Layer_Split is quite complicated feature, which splits a big image into twoparts and handles it by two layers and two scalers individually. But itimports an edge problem or effect in the middle of the image after the split.To avoid such a problem, it needs a complicated Split calculation and somespecial configurations to the layer and scaler. We’d better hide such HWrelated complexity to user mode.

• Slave pipeline, SeeDual pipeline with Slave enabled

  Since the compiz component doesn’t output alpha value, the slave pipelineonly can be used for bottom layers composition. The komeda driver wants tohide this limitation to the user. The way to do this is to pick a suitableLayer according to plane_state->zpos.

So for komeda, the KMS-plane doesn’t represent a fixed komeda layer pipeline,but multiple Layers with same capabilities. Komeda will select one or moreLayers to fit the requirement of one KMS-plane.

Make component/pipeline to be drm_private_obj¶

Adddrm_private_obj tokomeda_component,komeda_pipeline

structkomeda_component{structdrm_private_objobj;...}structkomeda_pipeline{structdrm_private_objobj;...}

Tracking component_state/pipeline_state by drm_atomic_state¶

Adddrm_private_state and user tokomeda_component_state,komeda_pipeline_state

structkomeda_component_state{structdrm_private_stateobj;void*binding_user;...}structkomeda_pipeline_state{structdrm_private_stateobj;structdrm_crtc*crtc;...}

komeda component validation¶

Komeda has multiple types of components, but the process of validation aresimilar, usually including the following steps:

intkomeda_xxxx_validate(structkomeda_component_xxxxxx_comp,structkomeda_component_output*input_dflow,structdrm_plane/crtc/connector*user,structdrm_plane/crtc/connector_state,*user_state){setup1:checkifcomponentisneeded,likethescalerisoptionaldependingontheuser_state;ifunneeded,justreturn,andthecallerwillputthedataflowintonextstage.Setup2:checkuser_statewithcomponentfeaturesandcapabilitiestoseeifrequirementscanbemet;ifnot,returnfail.Setup3:getcomponent_statefromdrm_atomic_state,andtrysettosetusertocomponent;failifcomponenthasbeenassignedtoanotheruseralready.Setup3:configurethecomponent_state,likesetitsinputcomponent,convertuser_statetocomponentspecificstate.Setup4:adjusttheinput_dflowandprepareitforthenextstage.}

komeda_kms Abstraction¶

structkomeda_plane¶

komeda instance of drm_plane

struct komeda_plane {    struct drm_plane base;    struct komeda_layer *layer;};

structkomeda_plane_state¶

struct komeda_plane_state {    struct drm_plane_state base;    struct list_head zlist_node;    u8 layer_split : 1;};

Description

The plane_state can be split into two data flow (left/right) and handledby two layerskomeda_plane.layer andkomeda_plane.layer.right

structkomeda_wb_connector¶

struct komeda_wb_connector {    struct drm_writeback_connector base;    struct komeda_layer *wb_layer;};

structkomeda_crtc¶

struct komeda_crtc {    struct drm_crtc base;    struct komeda_pipeline *master;    struct komeda_pipeline *slave;    u32 slave_planes;    struct komeda_wb_connector *wb_conn;    struct completion *disable_done;    struct drm_encoder encoder;};

structkomeda_crtc_state¶

struct komeda_crtc_state {    struct drm_crtc_state base;    u32 affected_pipes;    u32 active_pipes;    u64 clock_ratio;    u32 max_slave_zorder;};

komde_kms Functions¶

intkomeda_crtc_atomic_check(structdrm_crtc*crtc,structdrm_atomic_state*state)¶

build display output data flow

intkomeda_plane_atomic_check(structdrm_plane*plane,structdrm_atomic_state*state)¶

build input data flow