RISC-V Hardware Probing Interface¶

The RISC-V hardware probing interface is based around a single syscall, whichis defined in <asm/hwprobe.h>:

struct riscv_hwprobe {    __s64 key;    __u64 value;};long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count,                       size_t cpusetsize, cpu_set_t *cpus,                       unsigned int flags);

The arguments are split into three groups: an array of key-value pairs, a CPUset, and some flags. The key-value pairs are supplied with a count. Userspacemust prepopulate the key field for each element, and the kernel will fill in thevalue if the key is recognized. If a key is unknown to the kernel, its key fieldwill be cleared to -1, and its value set to 0. The CPU set is defined byCPU_SET(3) with sizecpusetsize bytes. For value-like keys (eg. vendor,arch, impl), the returned value will only be valid if all CPUs in the given sethave the same value. Otherwise -1 will be returned. For boolean-like keys, thevalue returned will be a logical AND of the values for the specified CPUs.Usermode can supply NULL forcpus and 0 forcpusetsize as a shortcut forall online CPUs. The currently supported flags are:

• RISCV_HWPROBE_WHICH_CPUS: This flag basically reverses the behaviorofsys_riscv_hwprobe(). Instead of populating the values of keys for a givenset of CPUs, the values of each key are given and the set of CPUs is reducedbysys_riscv_hwprobe() to only those which match each of the key-value pairs.How matching is done depends on the key type. For value-like keys, matchingmeans to be the exact same as the value. For boolean-like keys, matchingmeans the result of a logical AND of the pair’s value with the CPU’s value isexactly the same as the pair’s value. Additionally, whencpus is an emptyset, then it is initialized to all online CPUs which fit within it, i.e. theCPU set returned is the reduction of all the online CPUs which can berepresented with a CPU set of sizecpusetsize.

All other flags are reserved for future compatibility and must be zero.

On success 0 is returned, on failure a negative error code is returned.

The following keys are defined:

• RISCV_HWPROBE_KEY_MVENDORID: Contains the value ofmvendorid,as defined by the RISC-V privileged architecture specification.

• RISCV_HWPROBE_KEY_MARCHID: Contains the value ofmarchid, asdefined by the RISC-V privileged architecture specification.

• RISCV_HWPROBE_KEY_MIMPID: Contains the value ofmimpid, asdefined by the RISC-V privileged architecture specification.

• RISCV_HWPROBE_KEY_BASE_BEHAVIOR: A bitmask containing the baseuser-visible behavior that this kernel supports. The following base user ABIsare defined:

  • RISCV_HWPROBE_BASE_BEHAVIOR_IMA: Support for rv32ima orrv64ima, as defined by version 2.2 of the user ISA and version 1.10 of theprivileged ISA, with the following known exceptions (more exceptions may beadded, but only if it can be demonstrated that the user ABI is not broken):

    • Thefence.i instruction cannot be directly executed by userspaceprograms (it may still be executed in userspace via akernel-controlled mechanism such as the vDSO).

• RISCV_HWPROBE_KEY_IMA_EXT_0: A bitmask containing the extensionsthat are compatible with theRISCV_HWPROBE_BASE_BEHAVIOR_IMA:base system behavior.

  • RISCV_HWPROBE_IMA_FD: The F and D extensions are supported, asdefined by commit cd20cee (“FMIN/FMAX now implementminimumNumber/maximumNumber, not minNum/maxNum”) of the RISC-V ISA manual.

  • RISCV_HWPROBE_IMA_C: The C extension is supported, as definedby version 2.2 of the RISC-V ISA manual.

  • RISCV_HWPROBE_IMA_V: The V extension is supported, as defined byversion 1.0 of the RISC-V Vector extension manual.

  • RISCV_HWPROBE_EXT_ZBA: The Zba address generation extension is

    supported, as defined in version 1.0 of the Bit-Manipulation ISAextensions.

  • RISCV_HWPROBE_EXT_ZBB: The Zbb extension is supported, as defined

    in version 1.0 of the Bit-Manipulation ISA extensions.

  • RISCV_HWPROBE_EXT_ZBS: The Zbs extension is supported, as defined

    in version 1.0 of the Bit-Manipulation ISA extensions.

  • RISCV_HWPROBE_EXT_ZICBOZ: The Zicboz extension is supported, as

    ratified in commit 3dd606f (“Create cmobase-v1.0.pdf”) of riscv-CMOs.

  • RISCV_HWPROBE_EXT_ZBC The Zbc extension is supported, as defined

    in version 1.0 of the Bit-Manipulation ISA extensions.

  • RISCV_HWPROBE_EXT_ZBKB The Zbkb extension is supported, as

    defined in version 1.0 of the Scalar Crypto ISA extensions.

  • RISCV_HWPROBE_EXT_ZBKC The Zbkc extension is supported, as

    defined in version 1.0 of the Scalar Crypto ISA extensions.

  • RISCV_HWPROBE_EXT_ZBKX The Zbkx extension is supported, as

    defined in version 1.0 of the Scalar Crypto ISA extensions.

  • RISCV_HWPROBE_EXT_ZKND The Zknd extension is supported, as

    defined in version 1.0 of the Scalar Crypto ISA extensions.

  • RISCV_HWPROBE_EXT_ZKNE The Zkne extension is supported, as

    defined in version 1.0 of the Scalar Crypto ISA extensions.

  • RISCV_HWPROBE_EXT_ZKNH The Zknh extension is supported, as

    defined in version 1.0 of the Scalar Crypto ISA extensions.

  • RISCV_HWPROBE_EXT_ZKSED The Zksed extension is supported, as

    defined in version 1.0 of the Scalar Crypto ISA extensions.

  • RISCV_HWPROBE_EXT_ZKSH The Zksh extension is supported, as

    defined in version 1.0 of the Scalar Crypto ISA extensions.

  • RISCV_HWPROBE_EXT_ZKT The Zkt extension is supported, as defined

    in version 1.0 of the Scalar Crypto ISA extensions.

  • RISCV_HWPROBE_EXT_ZVBB: The Zvbb extension is supported as

    defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  • RISCV_HWPROBE_EXT_ZVBC: The Zvbc extension is supported as

    defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  • RISCV_HWPROBE_EXT_ZVKB: The Zvkb extension is supported as

    defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  • RISCV_HWPROBE_EXT_ZVKG: The Zvkg extension is supported as

    defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  • RISCV_HWPROBE_EXT_ZVKNED: The Zvkned extension is supported as

    defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  • RISCV_HWPROBE_EXT_ZVKNHA: The Zvknha extension is supported as

    defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  • RISCV_HWPROBE_EXT_ZVKNHB: The Zvknhb extension is supported as

    defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  • RISCV_HWPROBE_EXT_ZVKSED: The Zvksed extension is supported as

    defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  • RISCV_HWPROBE_EXT_ZVKSH: The Zvksh extension is supported as

    defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  • RISCV_HWPROBE_EXT_ZVKT: The Zvkt extension is supported as

    defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  • RISCV_HWPROBE_EXT_ZFH: The Zfh extension version 1.0 is supported

    as defined in the RISC-V ISA manual.

  • RISCV_HWPROBE_EXT_ZFHMIN: The Zfhmin extension version 1.0 is

    supported as defined in the RISC-V ISA manual.

  • RISCV_HWPROBE_EXT_ZIHINTNTL: The Zihintntl extension version 1.0

    is supported as defined in the RISC-V ISA manual.

  • RISCV_HWPROBE_EXT_ZVFH: The Zvfh extension is supported as

    defined in the RISC-V Vector manual starting fromcommit e2ccd0548d6c(“Remove draft warnings from Zvfh[min]”).

  • RISCV_HWPROBE_EXT_ZVFHMIN: The Zvfhmin extension is supported as

    defined in the RISC-V Vector manual starting fromcommit e2ccd0548d6c(“Remove draft warnings from Zvfh[min]”).

  • RISCV_HWPROBE_EXT_ZFA: The Zfa extension is supported as

    defined in the RISC-V ISA manual starting fromcommit 056b6ff467c7(“Zfa is ratified”).

  • RISCV_HWPROBE_EXT_ZTSO: The Ztso extension is supported as

    defined in the RISC-V ISA manual starting fromcommit 5618fb5a216b(“Ztso is now ratified.”)

  • RISCV_HWPROBE_EXT_ZACAS: The Zacas extension is supported as

    defined in the Atomic Compare-and-Swap (CAS) instructions manual startingfromcommit 5059e0ca641c (“update to ratified”).

  • RISCV_HWPROBE_EXT_ZICNTR: The Zicntr extension version 2.0

    is supported as defined in the RISC-V ISA manual.

  • RISCV_HWPROBE_EXT_ZICOND: The Zicond extension is supported as

    defined in the RISC-V Integer Conditional (Zicond) operations extensionmanual starting from commit 95cf1f9 (“Add changes requested by Vedduring signoff”)

  • RISCV_HWPROBE_EXT_ZIHINTPAUSE: The Zihintpause extension is

    supported as defined in the RISC-V ISA manual starting fromcommitd8ab5c78c207 (“Zihintpause is ratified”).

  • RISCV_HWPROBE_EXT_ZIHPM: The Zihpm extension version 2.0

    is supported as defined in the RISC-V ISA manual.

  • RISCV_HWPROBE_EXT_ZVE32X: The Vector sub-extension Zve32x issupported, as defined by version 1.0 of the RISC-V Vector extension manual.

  • RISCV_HWPROBE_EXT_ZVE32F: The Vector sub-extension Zve32f issupported, as defined by version 1.0 of the RISC-V Vector extension manual.

  • RISCV_HWPROBE_EXT_ZVE64X: The Vector sub-extension Zve64x issupported, as defined by version 1.0 of the RISC-V Vector extension manual.

  • RISCV_HWPROBE_EXT_ZVE64F: The Vector sub-extension Zve64f issupported, as defined by version 1.0 of the RISC-V Vector extension manual.

  • RISCV_HWPROBE_EXT_ZVE64D: The Vector sub-extension Zve64d issupported, as defined by version 1.0 of the RISC-V Vector extension manual.

  • RISCV_HWPROBE_EXT_ZIMOP: The Zimop May-Be-Operations extension is

    supported as defined in the RISC-V ISA manual starting from commit58220614a5f (“Zimop is ratified/1.0”).

  • RISCV_HWPROBE_EXT_ZCA: The Zca extension part of Zc* standard

    extensions for code size reduction, as ratified in commit 8be3419c1c0(“Zcf doesn’t exist on RV64 as it contains no instructions”) ofriscv-code-size-reduction.

  • RISCV_HWPROBE_EXT_ZCB: The Zcb extension part of Zc* standard

    extensions for code size reduction, as ratified in commit 8be3419c1c0(“Zcf doesn’t exist on RV64 as it contains no instructions”) ofriscv-code-size-reduction.

  • RISCV_HWPROBE_EXT_ZCD: The Zcd extension part of Zc* standard

    extensions for code size reduction, as ratified in commit 8be3419c1c0(“Zcf doesn’t exist on RV64 as it contains no instructions”) ofriscv-code-size-reduction.

  • RISCV_HWPROBE_EXT_ZCF: The Zcf extension part of Zc* standard

    extensions for code size reduction, as ratified in commit 8be3419c1c0(“Zcf doesn’t exist on RV64 as it contains no instructions”) ofriscv-code-size-reduction.

  • RISCV_HWPROBE_EXT_ZCMOP: The Zcmop May-Be-Operations extension is

    supported as defined in the RISC-V ISA manual starting from commitc732a4f39a4 (“Zcmop is ratified/1.0”).

  • RISCV_HWPROBE_EXT_ZAWRS: The Zawrs extension is supported as

    ratified incommit 98918c844281 (“Merge pull request #1217 fromriscv/zawrs”) of riscv-isa-manual.

  • RISCV_HWPROBE_EXT_ZAAMO: The Zaamo extension is supported as

    defined in the in the RISC-V ISA manual starting fromcommit e87412e621f1(“integrate Zaamo and Zalrsc text (#1304)”).

  • RISCV_HWPROBE_EXT_ZALASR: The Zalasr extension is supported as

    frozen at commit 194f0094 (“Version 0.9 for freeze”) of riscv-zalasr.

  • RISCV_HWPROBE_EXT_ZALRSC: The Zalrsc extension is supported as

    defined in the in the RISC-V ISA manual starting fromcommit e87412e621f1(“integrate Zaamo and Zalrsc text (#1304)”).

  • RISCV_HWPROBE_EXT_SUPM: The Supm extension is supported as

    defined in version 1.0 of the RISC-V Pointer Masking extensions.

  • RISCV_HWPROBE_EXT_ZFBFMIN: The Zfbfmin extension is supported as

    defined in the RISC-V ISA manual starting fromcommit 4dc23d6229de(“Added Chapter title to BF16”).

  • RISCV_HWPROBE_EXT_ZVFBFMIN: The Zvfbfmin extension is supported as

    defined in the RISC-V ISA manual starting fromcommit 4dc23d6229de(“Added Chapter title to BF16”).

  • RISCV_HWPROBE_EXT_ZVFBFWMA: The Zvfbfwma extension is supported as

    defined in the RISC-V ISA manual starting fromcommit 4dc23d6229de(“Added Chapter title to BF16”).

  • RISCV_HWPROBE_EXT_ZICBOM: The Zicbom extension is supported, as

    ratified in commit 3dd606f (“Create cmobase-v1.0.pdf”) of riscv-CMOs.

  • RISCV_HWPROBE_EXT_ZABHA: The Zabha extension is supported as

    ratified incommit 49f49c842ff9 (“Update to Rafified state”) ofriscv-zabha.

  • RISCV_HWPROBE_EXT_ZICBOP: The Zicbop extension is supported, as

    ratified in commit 3dd606f (“Create cmobase-v1.0.pdf”) of riscv-CMOs.

  • RISCV_HWPROBE_EXT_ZILSD: The Zilsd extension is supported as

    defined in the RISC-V ISA manual starting from commit f88abf1 (“Integratingload/store pair for RV32 with the main manual”) of the riscv-isa-manual.

  • RISCV_HWPROBE_EXT_ZCLSD: The Zclsd extension is supported as

    defined in the RISC-V ISA manual starting from commit f88abf1 (“Integratingload/store pair for RV32 with the main manual”) of the riscv-isa-manual.

• RISCV_HWPROBE_KEY_CPUPERF_0: Deprecated. Returns similar values to

  RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF, but the key wasmistakenly classified as a bitmask rather than a value.

• RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF: Anenumvalue describingthe performance of misaligned scalar native word accesses on the selected setof processors.

  • RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN: The performance ofmisaligned scalar accesses is unknown.

  • RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED: Misaligned scalaraccesses are emulated via software, either in or below the kernel. Theseaccesses are always extremely slow.

  • RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW: Misaligned scalar nativeword sized accesses are slower than the equivalent quantity of byteaccesses. Misaligned accesses may be supported directly in hardware, ortrapped and emulated by software.

  • RISCV_HWPROBE_MISALIGNED_SCALAR_FAST: Misaligned scalar nativeword sized accesses are faster than the equivalent quantity of byteaccesses.

  • RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED: Misaligned scalaraccesses are not supported at all and will generate a misaligned addressfault.

• RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE: An unsigned int whichrepresents the size of the Zicboz block in bytes.

• RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS: An unsigned long whichrepresent the highest userspace virtual address usable.

• RISCV_HWPROBE_KEY_TIME_CSR_FREQ: Frequency (in Hz) oftime CSR.

• RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF: An enum value describing the

  performance of misaligned vector accesses on the selected set of processors.

  • RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN: The performance of misalignedvector accesses is unknown.

  • RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW: 32-bit misaligned accesses using vectorregisters are slower than the equivalent quantity of byte accesses via vector registers.Misaligned accesses may be supported directly in hardware, or trapped and emulated by software.

  • RISCV_HWPROBE_MISALIGNED_VECTOR_FAST: 32-bit misaligned accesses using vectorregisters are faster than the equivalent quantity of byte accesses via vector registers.

  • RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED: Misaligned vector accesses arenot supported at all and will generate a misaligned address fault.

• RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0: A bitmask containing themips vendor extensions that are compatible with theRISCV_HWPROBE_BASE_BEHAVIOR_IMA: base system behavior.

  • MIPS

    • RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL: The xmipsexectl vendor

      extension is supported in the MIPS ISA extensions spec.

• RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: A bitmask containing thethead vendor extensions that are compatible with theRISCV_HWPROBE_BASE_BEHAVIOR_IMA: base system behavior.

  • T-HEAD

    • RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR: The xtheadvector vendor

      extension is supported in the T-Head ISA extensions spec starting fromcommit a18c801634 (“Add T-Head VECTOR vendor extension. “).

• RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE: An unsigned int whichrepresents the size of the Zicbom block in bytes.

• RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0: A bitmask containing thesifive vendor extensions that are compatible with theRISCV_HWPROBE_BASE_BEHAVIOR_IMA: base system behavior.

  • SIFIVE

    • RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD: The Xsfqmaccdod vendor

      extension is supported in version 1.1 of SiFive Int8 Matrix MultiplicationExtensions Specification.

    • RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ: The Xsfqmaccqoq vendor

      extension is supported in version 1.1 of SiFive Int8 Matrix MultiplicationInstruction Extensions Specification.

    • RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF: The Xsfvfnrclipxfqf

      vendor extension is supported in version 1.0 of SiFive FP32-to-int8 RangedClip Instructions Extensions Specification.

    • RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ: The Xsfvfwmaccqqq

      vendor extension is supported in version 1.0 of Matrix Multiply AccumulateInstruction Extensions Specification.

• RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE: An unsigned int whichrepresents the size of the Zicbop block in bytes.