Bus-Independent Device Accesses¶

Author:: Matthew Wilcox
Author:: Alan Cox

Introduction¶

Linux provides an API which abstracts performing IO across all busesand devices, allowing device drivers to be written independently of bustype.

Memory Mapped IO¶

Getting Access to the Device¶

The most widely supported form of IO is memory mapped IO. That is, apart of the CPU’s address space is interpreted not as accesses tomemory, but as accesses to a device. Some architectures define devicesto be at a fixed address, but most have some method of discoveringdevices. The PCI bus walk is a good example of such a scheme. Thisdocument does not cover how to receive such an address, but assumes youare starting with one. Physical addresses are of type unsigned long.

This address should not be used directly. Instead, to get an addresssuitable for passing to the accessor functions described below, youshould callioremap(). An address suitable for accessingthe device will be returned to you.

After you’ve finished using the device (say, in your module’s exitroutine), calliounmap() in order to return the addressspace to the kernel. Most architectures allocate new address space eachtime you callioremap(), and they can run out unless youcalliounmap().

Accessing the device¶

The part of the interface most used by drivers is reading and writingmemory-mapped registers on the device. Linux provides interfaces to readand write 8-bit, 16-bit, 32-bit and 64-bit quantities. Due to ahistorical accident, these are named byte, word, long and quad accesses.Both read and write accesses are supported; there is no prefetch supportat this time.

The functions are namedreadb(),readw(),readl(),readq(),readb_relaxed(),readw_relaxed(),readl_relaxed(),readq_relaxed(),writeb(),writew(),writel() andwriteq().

Some devices (such as framebuffers) would like to use larger transfers than8 bytes at a time. For these devices, thememcpy_toio(),memcpy_fromio() andmemset_io() functions areprovided. Do not use memset or memcpy on IO addresses; they are notguaranteed to copy data in order.

The read and write functions are defined to be ordered. That is thecompiler is not permitted to reorder the I/O sequence. When the orderingcan be compiler optimised, you can use__readb() and friends toindicate the relaxed ordering. Use this with care.

While the basic functions are defined to be synchronous with respect toeach other and ordered with respect to each other the buses the devicessit on may themselves have asynchronicity. In particular many authorsare burned by the fact that PCI bus writes are posted asynchronously. Adriver author must issue a read from the same device to ensure thatwrites have occurred in the specific cases the author cares. This kindof property cannot be hidden from driver writers in the API. In somecases, the read used to flush the device may be expected to fail (if thecard is resetting, for example). In that case, the read should be donefrom config space, which is guaranteed to soft-fail if the card doesn’trespond.

The following is an example of flushing a write to a device when thedriver would like to ensure the write’s effects are visible prior tocontinuing execution:

static inline voidqla1280_disable_intrs(struct scsi_qla_host *ha){    struct device_reg *reg;    reg = ha->iobase;    /* disable risc and host interrupts */    WRT_REG_WORD(&reg->ictrl, 0);    /*     * The following read will ensure that the above write     * has been received by the device before we return from this     * function.     */    RD_REG_WORD(&reg->ictrl);    ha->flags.ints_enabled = 0;}

PCI ordering rules also guarantee that PIO read responses arrive after anyoutstanding DMA writes from that bus, since for some devices the result ofareadb() call may signal to the driver that a DMA transaction iscomplete. In many cases, however, the driver may want to indicate that thenextreadb() call has no relation to any previous DMA writesperformed by the device. The driver can usereadb_relaxed() forthese cases, although only some platforms will honor the relaxedsemantics. Using the relaxed read functions will provide significantperformance benefits on platforms that support it. The qla2xxx driverprovides examples of how to usereadX_relaxed(). In many cases, a majorityof the driver’sreadX() calls can safely be converted toreadX_relaxed()calls, since only a few will indicate or depend on DMA completion.

Port Space Accesses¶

Port Space Explained¶

Another form of IO commonly supported is Port Space. This is a range ofaddresses separate to the normal memory address space. Access to theseaddresses is generally not as fast as accesses to the memory mappedaddresses, and it also has a potentially smaller address space.

Unlike memory mapped IO, no preparation is required to access portspace.

Accessing Port Space¶

Accesses to this space are provided through a set of functions whichallow 8-bit, 16-bit and 32-bit accesses; also known as byte, word andlong. These functions areinb(),inw(),inl(),outb(),outw() andoutl().

Some variants are provided for these functions. Some devices requirethat accesses to their ports are slowed down. This functionality isprovided by appending a_p to the end of the function.There are also equivalents to memcpy. Theins() andouts() functions copy bytes, words or longs to the givenport.

__iomem pointer tokens¶

The data type for an MMIO address is an__iomem qualified pointer, such asvoid__iomem*reg. On most architectures it is a regular pointer thatpoints to a virtual memory address and can be offset or dereferenced, but inportable code, it must only be passed from and to functions that explicitlyoperated on an__iomem token, in particular theioremap() andreadl()/writel() functions. The ‘sparse’ semantic code checker can be used toverify that this is done correctly.

While on most architectures,ioremap() creates a page table entry for anuncached virtual address pointing to the physical MMIO address, somearchitectures require special instructions for MMIO, and the__iomem pointerjust encodes the physical address or an offsettable cookie that is interpretedbyreadl()/writel().

Differences between I/O access functions¶

readq(),readl(),readw(),readb(),writeq(),writel(),writew(),writeb()

These are the most generic accessors, providing serialization against otherMMIO accesses and DMA accesses as well as fixed endianness for accessinglittle-endian PCI devices and on-chip peripherals. Portable device driversshould generally use these for any access to__iomem pointers.
Note that posted writes are not strictly ordered against a spinlock, seeOrdering I/O writes to memory-mapped addresses.

readq_relaxed(),readl_relaxed(),readw_relaxed(),readb_relaxed(),writeq_relaxed(),writel_relaxed(),writew_relaxed(),writeb_relaxed()

On architectures that require an expensive barrier for serializing againstDMA, these “relaxed” versions of the MMIO accessors only serialize againsteach other, but contain a less expensive barrier operation. A device drivermight use these in a particularly performance sensitive fast path, with acomment that explains why the usage in a specific location is safe withoutthe extra barriers.
See memory-barriers.txt for a more detailed discussion on the precise orderingguarantees of the non-relaxed and relaxed versions.

ioread64(),ioread32(),ioread16(),ioread8(),iowrite64(),iowrite32(),iowrite16(),iowrite8()

These are an alternative to the normalreadl()/writel() functions, with almostidentical behavior, but they can also operate on__iomem tokens returnedfor mapping PCI I/O space withpci_iomap() orioport_map(). On architecturesthat require special instructions for I/O port access, this adds a smalloverhead for an indirect function call implemented in lib/iomap.c, while onother architectures, these are simply aliases.

ioread64be(),ioread32be(),ioread16be()iowrite64be(),iowrite32be(),iowrite16be()

These behave in the same way as theioread32()/iowrite32() family, but withreversed byte order, for accessing devices with big-endian MMIO registers.Device drivers that can operate on either big-endian or little-endianregisters may have to implement a custom wrapper function that picks one orthe other depending on which device was found.
Note: On some architectures, the normalreadl()/writel() functionstraditionally assume that devices are the same endianness as the CPU, whileusing a hardware byte-reverse on the PCI bus when running a big-endian kernel.Drivers that usereadl()/writel() this way are generally not portable, buttend to be limited to a particular SoC.

hi_lo_readq(),lo_hi_readq(),hi_lo_readq_relaxed(),lo_hi_readq_relaxed(),ioread64_lo_hi(),ioread64_hi_lo(),ioread64be_lo_hi(),ioread64be_hi_lo(),hi_lo_writeq(),lo_hi_writeq(),hi_lo_writeq_relaxed(),lo_hi_writeq_relaxed(),iowrite64_lo_hi(),iowrite64_hi_lo(),iowrite64be_lo_hi(),iowrite64be_hi_lo()

Some device drivers have 64-bit registers that cannot be accessed atomicallyon 32-bit architectures but allow two consecutive 32-bit accesses instead.Since it depends on the particular device which of the two halves has to beaccessed first, a helper is provided for each combination of 64-bit accessorswith either low/high or high/low word ordering. A device driver must includeeither <linux/io-64-nonatomic-lo-hi.h> or <linux/io-64-nonatomic-hi-lo.h> toget the function definitions along with helpers that redirect the normalreadq()/writeq() to them on architectures that do not provide 64-bit accessnatively.

__raw_readq(),__raw_readl(),__raw_readw(),__raw_readb(),__raw_writeq(),__raw_writel(),__raw_writew(),__raw_writeb()

These are low-level MMIO accessors without barriers or byteorder changes andarchitecture specific behavior. Accesses are usually atomic in the sense thata four-byte__raw_readl() does not get split into individual byte loads, butmultiple consecutive accesses can be combined on the bus. In portable code, itis only safe to use these to access memory behind a device bus but not MMIOregisters, as there are no ordering guarantees with regard to other MMIOaccesses or even spinlocks. The byte order is generally the same as for normalmemory, so unlike the other functions, these can be used to copy data betweenkernel memory and device memory.

inl(),inw(),inb(),outl(),outw(),outb()

PCI I/O port resources traditionally require separate helpers as they areimplemented using special instructions on the x86 architecture. On most otherarchitectures, these are mapped toreadl()/writel() style accessorsinternally, usually pointing to a fixed area in virtual memory. Instead of an__iomem pointer, the address is a 32-bit integer token to identify a portnumber. PCI requires I/O port access to be non-posted, meaning that anoutb()must complete before the following code executes, while a normalwriteb() maystill be in progress. On architectures that correctly implement this, I/O portaccess is therefore ordered against spinlocks. Many non-x86 PCI host bridgeimplementations and CPU architectures however fail to implement non-posted I/Ospace on PCI, so they can end up being posted on such hardware.
In some architectures, the I/O port number space has a 1:1 mapping to__iomem pointers, but this is not recommended and device drivers shouldnot rely on that for portability. Similarly, an I/O port number as describedin a PCI base address register may not correspond to the port number as seenby a device driver. Portable drivers need to read the port number for theresource provided by the kernel.
There are no direct 64-bit I/O port accessors, butpci_iomap() in combinationwith ioread64/iowrite64 can be used instead.

inl_p(),inw_p(),inb_p(),outl_p(),outw_p(),outb_p()

On ISA devices that require specific timing, the _p versions of the I/Oaccessors add a small delay. On architectures that do not have ISA buses,these are aliases to the normal inb/outb helpers.

readsq, readsl, readsw, readsbwritesq, writesl, writesw, writesbioread64_rep, ioread32_rep, ioread16_rep, ioread8_repiowrite64_rep, iowrite32_rep, iowrite16_rep, iowrite8_repinsl, insw, insb, outsl, outsw, outsb

These are helpers that access the same address multiple times, usually to copydata between kernel memory byte stream and a FIFO buffer. Unlike the normalMMIO accessors, these do not perform a byteswap on big-endian kernels, so thefirst byte in the FIFO register corresponds to the first byte in the memorybuffer regardless of the architecture.

Device memory mapping modes¶

Some architectures support multiple modes for mapping device memory.ioremap_*() variants provide a common abstraction around thesearchitecture-specific modes, with a shared set of semantics.

ioremap() is the most common mapping type, and is applicable to typical devicememory (e.g. I/O registers). Other modes can offer weaker or strongerguarantees, if supported by the architecture. From most to least common, theyare as follows:

ioremap()¶

The default mode, suitable for most memory-mapped devices, e.g. controlregisters. Memory mapped usingioremap() has the following characteristics:

Uncached - CPU-side caches are bypassed, and all reads and writes are handleddirectly by the device
No speculative operations - the CPU may not issue a read or write to thismemory, unless the instruction that does so has been reached in committedprogram flow.
No reordering - The CPU may not reorder accesses to this memory mapping withrespect to each other. On some architectures, this relies on barriers inreadl_relaxed()/writel_relaxed().
No repetition - The CPU may not issue multiple reads or writes for a singleprogram instruction.
No write-combining - Each I/O operation results in one discrete read or writebeing issued to the device, and multiple writes are not combined into largerwrites. This may or may not be enforced when using __raw I/O accessors orpointer dereferences.
Non-executable - The CPU is not allowed to speculate instruction executionfrom this memory (it probably goes without saying, but you’re also notallowed to jump into device memory).

On many platforms and buses (e.g. PCI), writes issued throughioremap()mappings are posted, which means that the CPU does not wait for the write toactually reach the target device before retiring the write instruction.

On many platforms, I/O accesses must be aligned with respect to the accesssize; failure to do so will result in an exception or unpredictable results.

ioremap_wc()¶

Maps I/O memory as normal memory with write combining. Unlikeioremap(),

The CPU may speculatively issue reads from the device that the programdidn’t actually execute, and may choose to basically read whatever it wants.
The CPU may reorder operations as long as the result is consistent from theprogram’s point of view.
The CPU may write to the same location multiple times, even when the programissued a single write.
The CPU may combine several writes into a single larger write.

This mode is typically used for video framebuffers, where it can increaseperformance of writes. It can also be used for other blocks of memory indevices (e.g. buffers or shared memory), but care must be taken as accesses arenot guaranteed to be ordered with respect to normalioremap() MMIO registeraccesses without explicit barriers.

On a PCI bus, it is usually safe to useioremap_wc() on MMIO areas marked asIORESOURCE_PREFETCH, but it may not be used on those without the flag.For on-chip devices, there is no corresponding flag, but a driver can useioremap_wc() on a device that is known to be safe.

ioremap_wt()¶

Maps I/O memory as normal memory with write-through caching. Likeioremap_wc(),but also,

The CPU may cache writes issued to and reads from the device, and serve readsfrom that cache.

This mode is sometimes used for video framebuffers, where drivers still expectwrites to reach the device in a timely manner (and not be stuck in the CPUcache), but reads may be served from the cache for efficiency. However, it israrely useful these days, as framebuffer drivers usually perform writes only,for whichioremap_wc() is more efficient (as it doesn’t needlessly trash thecache). Most drivers should not use this.

ioremap_np()¶

Likeioremap(), but explicitly requests non-posted write semantics. On somearchitectures and buses,ioremap() mappings have posted write semantics, whichmeans that writes can appear to “complete” from the point of view of theCPU before the written data actually arrives at the target device. Writes arestill ordered with respect to other writes and reads from the same device, butdue to the posted write semantics, this is not the case with respect to otherdevices.ioremap_np() explicitly requests non-posted semantics, which meansthat the write instruction will not appear to complete until the device hasreceived (and to some platform-specific extent acknowledged) the written data.

This mapping mode primarily exists to cater for platforms with bus fabrics thatrequire this particular mapping mode to work correctly. These platforms set theIORESOURCE_MEM_NONPOSTED flag for a resource that requiresioremap_np()semantics and portable drivers should use an abstraction that automaticallyselects it where appropriate (see theHigher-level ioremap abstractionssection below).

The bareioremap_np() is only available on some architectures; on others, italways returns NULL. Drivers should not normally use it, unless they areplatform-specific or they derive benefit from non-posted writes wheresupported, and can fall back toioremap() otherwise. The normal approach toensure posted write completion is to do a dummy read after a write asexplained inAccessing the device, which works withioremap() on allplatforms.

ioremap_np() should never be used for PCI drivers. PCI memory space writes arealways posted, even on architectures that otherwise implementioremap_np().Usingioremap_np() for PCI BARs will at best result in posted write semantics,and at worst result in complete breakage.

Note that non-posted write semantics are orthogonal to CPU-side orderingguarantees. A CPU may still choose to issue other reads or writes before anon-posted write instruction retires. See the previous section on MMIO accessfunctions for details on the CPU side of things.

ioremap_uc()¶

ioremap_uc() is only meaningful on old x86-32 systems with the PAT extension,and on ia64 with its slightly unconventionalioremap() behavior, everywhereelssioremap_uc() defaults to return NULL.

Portable drivers should avoid the use ofioremap_uc(), useioremap() instead.

ioremap_cache()¶

ioremap_cache() effectively maps I/O memory as normal RAM. CPU write-backcaches can be used, and the CPU is free to treat the device as if it were ablock of RAM. This should never be used for device memory which has sideeffects of any kind, or which does not return the data previously written onread.

It should also not be used for actual RAM, as the returned pointer is an__iomem token.memremap() can be used for mapping normal RAM that is outsideof the linear kernel memory area to a regular pointer.

Portable drivers should avoid the use ofioremap_cache().

Architecture example¶

Here is how the above modes map to memory attribute settings on the ARM64architecture:

API	Memory region type and cacheability
`ioremap_np()`	Device-nGnRnE
`ioremap()`	Device-nGnRE
`ioremap_uc()`	(not implemented)
`ioremap_wc()`	Normal-Non Cacheable
`ioremap_wt()`	(not implemented; fallback to ioremap)
`ioremap_cache()`	Normal-Write-Back Cacheable

Higher-level ioremap abstractions¶

Instead of using the above rawioremap() modes, drivers are encouraged to usehigher-level APIs. These APIs may implement platform-specific logic toautomatically choose an appropriate ioremap mode on any given bus, allowing fora platform-agnostic driver to work on those platforms without any specialcases. At the time of this writing, the followingioremap() wrappers have suchlogic:

devm_ioremap_resource()

Can automatically selectioremap_np() overioremap() according to platformrequirements, if theIORESOURCE_MEM_NONPOSTED flag is set on thestructresource. Uses devres to automatically unmap the resource when the driverprobe() function fails or a device in unbound from its driver.
Documented inDevres - Managed Device Resource.

of_address_to_resource()

Automatically sets theIORESOURCE_MEM_NONPOSTED flag for platforms thatrequire non-posted writes for certain buses (see the nonposted-mmio andposted-mmio device tree properties).

of_iomap()

Maps the resource described in areg property in the device tree, doingall required translations. Automatically selectsioremap_np() according toplatform requirements, as above.

pci_ioremap_bar(),pci_ioremap_wc_bar()

Maps the resource described in a PCI base address without having to extractthe physical address first.

pci_iomap(),pci_iomap_wc()

Likepci_ioremap_bar()/pci_ioremap_bar(), but also works on I/O space whenused together withioread32()/iowrite32() and similar accessors

pcim_iomap()

Likepci_iomap(), but uses devres to automatically unmap the resource whenthe driverprobe() function fails or a device in unbound from its driver
Documented inDevres - Managed Device Resource.

Not using these wrappers may make drivers unusable on certain platforms withstricter rules for mapping I/O memory.

Generalizing Access to System and I/O Memory¶

When accessing a memory region, depending on its location, users may have toaccess it with I/O operations or memory load/store operations. For example,copying to system memory could be done withmemcpy(), copying to I/O memorywould be done withmemcpy_toio().

void*vaddr=...;// pointer to system memorymemcpy(vaddr,src,len);void*vaddr_iomem=...;// pointer to I/O memorymemcpy_toio(vaddr_iomem,src,len);

The user of such pointer may not have information about the mapping of thatregion or may want to have a single code path to handle operations on thatbuffer, regardless if it’s located in system or IO memory. The typestructiosys_map and its helpers abstract that so thebuffer can be passed around to other drivers or have separate duties insidethe same driver for allocation, read and write operations.

Open-coding access tostructiosys_map is consideredbad style. Rather than accessing its fields directly, use one of the providedhelper functions, or implement your own. For example, instances ofstructiosys_map can be initialized statically withIOSYS_MAP_INIT_VADDR(), or at runtime withiosys_map_set_vaddr(). Thesehelpers will set an address in system memory.

structiosys_mapmap=IOSYS_MAP_INIT_VADDR(0xdeadbeaf);iosys_map_set_vaddr(&map,0xdeadbeaf);

To set an address in I/O memory, useIOSYS_MAP_INIT_VADDR_IOMEM() oriosys_map_set_vaddr_iomem().

structiosys_mapmap=IOSYS_MAP_INIT_VADDR_IOMEM(0xdeadbeaf);iosys_map_set_vaddr_iomem(&map,0xdeadbeaf);

Instances ofstructiosys_map do not have to be cleaned up, butcan be cleared to NULL withiosys_map_clear(). Cleared mappingsalways refer to system memory.

iosys_map_clear(&map);

Test if a mapping is valid with eitheriosys_map_is_set() oriosys_map_is_null().

if(iosys_map_is_set(&map)!=iosys_map_is_null(&map))// always true

Instances ofstructiosys_map can be compared forequality withiosys_map_is_equal(). Mappings that point to different memoryspaces, system or I/O, are never equal. That’s even true if both spaces arelocated in the same address space, both mappings contain the same addressvalue, or both mappings refer to NULL.

structiosys_mapsys_map;// refers to system memorystructiosys_mapio_map;// refers to I/O memoryif(iosys_map_is_equal(&sys_map,&io_map))// always false

A set up instance ofstructiosys_map can be used to access or manipulate thebuffer memory. Depending on the location of the memory, the provided helperswill pick the correct operations. Data can be copied into the memory withiosys_map_memcpy_to(). The address can be manipulated withiosys_map_incr().

constvoid*src=...;// source buffersize_tlen=...;// length of srciosys_map_memcpy_to(&map,src,len);iosys_map_incr(&map,len);// go to first byte after the memcpy

structiosys_map¶: Pointer to IO/system memory

Definition:

struct iosys_map {    union {        void __iomem *vaddr_iomem;        void *vaddr;    };    bool is_iomem;};

Members

{unnamed_union}: anonymous
vaddr_iomem: The buffer’s address if in I/O memory
vaddr: The buffer’s address if in system memory
is_iomem: True if the buffer is located in I/O memory, or falseotherwise.

IOSYS_MAP_INIT_VADDR¶

IOSYS_MAP_INIT_VADDR(vaddr_)

Initializesstructiosys_map to an address in system memory

Parameters

vaddr_: A system-memory address

IOSYS_MAP_INIT_VADDR_IOMEM¶

IOSYS_MAP_INIT_VADDR_IOMEM(vaddr_iomem_)

Initializesstructiosys_map to an address in I/O memory

Parameters

vaddr_iomem_: An I/O-memory address

IOSYS_MAP_INIT_OFFSET¶

IOSYS_MAP_INIT_OFFSET(map_,offset_)

Initializesstructiosys_map from another iosys_map

Parameters

map_: The dma-buf mapping structure to copy from
offset_: Offset to add to the other mapping

Description

Initializes a new iosys_mapstructbased on another passed as argument. Itdoes a shallow copy of thestructso it’s possible to update the back storagewithout changing where the original map points to. It is the equivalent ofdoing:

iosys_mapmap=other_map;iosys_map_incr(&map,&offset);

Example usage:

voidfoo(structdevice*dev,structiosys_map*base_map){...structiosys_mapmap=IOSYS_MAP_INIT_OFFSET(base_map,FIELD_OFFSET);...}

The advantage of using the initializer over just increasing the offset withiosys_map_incr() like above is that the new map will always point to theright place of the buffer during its scope. It reduces the risk of updatingthe wrong part of the buffer and having no compiler warning about that. Ifthe assignment toIOSYS_MAP_INIT_OFFSET() is forgotten, the compiler can warnabout the use of uninitialized variable.

voidiosys_map_set_vaddr(structiosys_map*map,void*vaddr)¶: Sets a iosys mapping structure to an address in system memory

Parameters

structiosys_map*map: The iosys_map structure
void*vaddr: A system-memory address

Description

Sets the address and clears the I/O-memory flag.

voidiosys_map_set_vaddr_iomem(structiosys_map*map,void__iomem*vaddr_iomem)¶: Sets a iosys mapping structure to an address in I/O memory

Parameters

structiosys_map*map: The iosys_map structure
void__iomem*vaddr_iomem: An I/O-memory address

Description

Sets the address and the I/O-memory flag.

booliosys_map_is_equal(conststructiosys_map*lhs,conststructiosys_map*rhs)¶: Compares two iosys mapping structures for equality

Parameters

conststructiosys_map*lhs: The iosys_map structure
conststructiosys_map*rhs: A iosys_map structure to compare with

Description

Two iosys mapping structures are equal if they both refer to the same type of memoryand to the same address within that memory.

Return

True is both structures are equal, or false otherwise.

booliosys_map_is_null(conststructiosys_map*map)¶: Tests for a iosys mapping to be NULL

Parameters

conststructiosys_map*map: The iosys_map structure

Description

Depending on the state ofstructiosys_map.is_iomem, tests if themapping is NULL.

Return

True if the mapping is NULL, or false otherwise.

booliosys_map_is_set(conststructiosys_map*map)¶: Tests if the iosys mapping has been set

Parameters

conststructiosys_map*map: The iosys_map structure

Description

Depending on the state ofstructiosys_map.is_iomem, tests if themapping has been set.

Return

True if the mapping is been set, or false otherwise.

voidiosys_map_clear(structiosys_map*map)¶: Clears a iosys mapping structure

Parameters

structiosys_map*map: The iosys_map structure

Description

Clears all fields to zero, includingstructiosys_map.is_iomem, somapping structures that were set to point to I/O memory are reset forsystem memory. Pointers are cleared to NULL. This is the default.

voidiosys_map_memcpy_to(structiosys_map*dst,size_tdst_offset,constvoid*src,size_tlen)¶: Memcpy into offset of iosys_map

Parameters

structiosys_map*dst: The iosys_map structure
size_tdst_offset: The offset from which to copy
constvoid*src: The source buffer
size_tlen: The number of byte in src

Description

Copies data into a iosys_map with an offset. The source buffer is insystem memory. Depending on the buffer’s location, the helper picks thecorrect method of accessing the memory.

voidiosys_map_memcpy_from(void*dst,conststructiosys_map*src,size_tsrc_offset,size_tlen)¶: Memcpy from iosys_map into system memory

Parameters

void*dst: Destination in system memory
conststructiosys_map*src: The iosys_map structure
size_tsrc_offset: The offset from which to copy
size_tlen: The number of byte in src

Description

Copies data from a iosys_map with an offset. The dest buffer is insystem memory. Depending on the mapping location, the helper picks thecorrect method of accessing the memory.

voidiosys_map_incr(structiosys_map*map,size_tincr)¶: Increments the address stored in a iosys mapping

Parameters

structiosys_map*map: The iosys_map structure
size_tincr: The number of bytes to increment

Description

Increments the address stored in a iosys mapping. Depending on thebuffer’s location, the correct value will be updated.

voidiosys_map_memset(structiosys_map*dst,size_toffset,intvalue,size_tlen)¶: Memset iosys_map

Parameters

structiosys_map*dst: The iosys_map structure
size_toffset: Offset from dst where to start setting value
intvalue: The value to set
size_tlen: The number of bytes to set in dst

Description

Set value in iosys_map. Depending on the buffer’s location, the helperpicks the correct method of accessing the memory.

iosys_map_rd¶

iosys_map_rd(map__,offset__,type__)

Read a C-type value from the iosys_map

Parameters

map__: The iosys_map structure
offset__: The offset from which to read
type__: Type of the value being read

Description

Read a C type value (u8, u16, u32 and u64) from iosys_map. For other types orif pointer may be unaligned (and problematic for the architecture supported),useiosys_map_memcpy_from().

Return

The value read from the mapping.

iosys_map_wr¶

iosys_map_wr(map__,offset__,type__,val__)

Write a C-type value to the iosys_map

Parameters

map__: The iosys_map structure
offset__: The offset from the mapping to write to
type__: Type of the value being written
val__: Value to write

Description

Write a C type value (u8, u16, u32 and u64) to the iosys_map. For other typesor if pointer may be unaligned (and problematic for the architecturesupported), useiosys_map_memcpy_to()

iosys_map_rd_field¶

iosys_map_rd_field(map__,struct_offset__,struct_type__,field__)

Read a member from astructin the iosys_map

Parameters

map__: The iosys_map structure
struct_offset__: Offset from the beginning of the map, where thestructis located
struct_type__: Thestructdescribing the layout of the mapping
field__: Member of thestructto read

Description

Read a value from iosys_map considering its layout is described by a Cstructstarting atstruct_offset__. The field offset and size is calculated and itsvalue read. If the field access would incur in un-aligned access, then eitheriosys_map_memcpy_from() needs to be used or the architecture must support it.For example: suppose there is astruct foo defined as below and the valuefoo.field2.inner2 needs to be read from the iosys_map:

structfoo{intfield1;struct{intinner1;intinner2;}field2;intfield3;}__packed;

This is the expected memory layout of a buffer usingiosys_map_rd_field():

Address	Content
buffer + 0000	start of mmapped bufferpointed by iosys_map
...	...
buffer +`struct_offset__`	start of`structfoo`
...	...
buffer + wwww	`foo.field2.inner2`
...	...
buffer + yyyy	end of`structfoo`
...	...
buffer + zzzz	end of mmaped buffer

Values automatically calculated by this macro or not needed are denoted bywwww, yyyy and zzzz. This is the code to read that value:

x=iosys_map_rd_field(&map,offset,structfoo,field2.inner2);

Return

The value read from the mapping.

iosys_map_wr_field¶

iosys_map_wr_field(map__,struct_offset__,struct_type__,field__,val__)

Write to a member of astructin the iosys_map

Parameters

map__: The iosys_map structure
struct_offset__: Offset from the beginning of the map, where thestructis located
struct_type__: Thestructdescribing the layout of the mapping
field__: Member of thestructto read
val__: Value to write

Description

Write a value to the iosys_map considering its layout is described by a Cstructstarting atstruct_offset__. The field offset and size is calculatedand theval__ is written. If the field access would incur in un-alignedaccess, then eitheriosys_map_memcpy_to() needs to be used or thearchitecture must support it. Refer toiosys_map_rd_field() for expectedusage and memory layout.

Public Functions Provided¶

phys_addr_tvirt_to_phys(volatilevoid*address)¶: map virtual addresses to physical

Parameters

volatilevoid*address: address to remap

Description

The returned physical address is the physical (CPU) mapping forthe memory address given. It is only valid to use this function onaddresses directly mapped or allocated via kmalloc.
This function does not give bus mappings for DMA transfers. Inalmost all conceivable cases a device driver should not be usingthis function

void*phys_to_virt(phys_addr_taddress)¶: map physical address to virtual

Parameters

phys_addr_taddress: address to remap

Description

The returned virtual address is a current CPU mapping forthe memory address given. It is only valid to use this function onaddresses that have a kernel mapping
This function does not handle bus mappings for DMA transfers. Inalmost all conceivable cases a device driver should not be usingthis function

void__iomem*ioremap(resource_size_toffset,unsignedlongsize)¶: map bus memory into CPU space

Parameters

resource_size_toffset: bus address of the memory
unsignedlongsize: size of the resource to map

Description

ioremap performs a platform specific sequence of operations tomake bus memory CPU accessible via the readb/readw/readl/writeb/writew/writel functions and the other mmio helpers. The returnedaddress is not guaranteed to be usable directly as a virtualaddress.

If the area you are trying to map is a PCI BAR you should have alook atpci_iomap().

voidiosubmit_cmds512(void__iomem*dst,constvoid*src,size_tcount)¶: copy data to single MMIO location, in 512-bit units

Parameters

void__iomem*dst: destination, in MMIO space (must be 512-bit aligned)
constvoid*src: source
size_tcount: number of 512 bits quantities to submit

Description

Submit data from kernel space to MMIO space, in units of 512 bits at atime. Order of access is not guaranteed, nor is a memory barrierperformed afterwards.

Warning: Do not use this helper unless your driver has checked that the CPUinstruction is supported on the platform.

Movatterモバイル変換

Bus-Independent Device Accesses¶

Introduction¶

Memory Mapped IO¶

Getting Access to the Device¶

Accessing the device¶

Port Space Accesses¶

Port Space Explained¶

Accessing Port Space¶

__iomem pointer tokens¶

Differences between I/O access functions¶

Device memory mapping modes¶

ioremap()¶

ioremap_wc()¶

ioremap_wt()¶

ioremap_np()¶

ioremap_uc()¶

ioremap_cache()¶

Architecture example¶

Higher-level ioremap abstractions¶

Generalizing Access to System and I/O Memory¶

Public Functions Provided¶