SPI wiring modes¶

These ADCs can output data on several SDO lines (1/2/4/8). The drivercurrently supports only 1 SDO line.

SPI offload wiring¶

When used with a SPI offload, the supported wiring configuration is:

+-------------+         +-------------+|        BUSY |-------->| TRIGGER     ||          CS |<--------| CS          ||             |         |             ||     ADC     |         |     SPI     ||             |         |             ||         SDI |<--------| SDO         ||       DOUTA |-------->| SDI         ||        SCLK |<--------| SCLK        ||             |         |             ||             |         +-------------+|      CONVST |<--------| PWM         |+-------------+         +-------------+

In this case, thepwms property is required.The#trigger-source-cells=<1> property is also required to connect backto the SPI offload. The SPI offload will havetrigger-sources propertywith a cell to indicate the busy signal:<&ad7606AD4695_TRIGGER_EVENT_BUSY>.

Parallel wiring mode¶

There is also a parallel interface, with 16 lines (that can be reduced to 8 inbyte mode). The parallel interface is selected by declaring the device asplatform in the device tree (with no io-backends node defined, see below).

IIO-backend mode¶

This mode allows to reach the best sample rates, but it requires an externalhardware (eg HDL or APU) to handle the low level communication.The backend mode is enabled when through the definition of the “io-backends”property in the device tree.

The reference configuration for the current implementation of IIO-backend modeis the HDL reference provided by ADI:https://wiki.analog.com/resources/eval/user-guides/ad7606x-fmc/hdl

This implementation embeds an IIO-backend compatible IP (adi-axi-adc) and a PWMconnected to the conversion trigger pin.

+---+                                       +----------------------------|   |               +-------+               |AD76xx| A |  controls     |       |               || D |-------------->|  PWM  |-------------->| cnvst| 7 |               |       |               || 6 |               +-------+               || 0 | controls  +-----------+-----------+   || 6 |---------->|           |           |<--| frstdata|   |           | Backend   |  Backend  |<--| busy| D |           | Driver    |           |   || R |           |           |           |-->| clk| I |  requests |+---------+| DMA       |   || V |----------->|  Buffer ||<----      |<=>| DATA| E |           |+---------+|           |   || R |           +-----------+-----------+   ||   |-------------------------------------->| reset/configuration gpios+---+                                       +-----------------------------

Software and hardware modes¶

While all the AD7606/AD7616 series parts can be configured using GPIOs, some ofthem can be configured using register.

The chips that support software mode have more values available for configuringthe device, as well as more settings, and allow to control the range andcalibration per channel.

The following settings are available per channel in software mode:

• Scale

Also, there is a broader choice of oversampling ratios in software mode.

Conversion triggering¶

The conversion can be triggered by two distinct ways:

• A GPIO is connected to the conversion trigger pin, and this GPIO is controlledby the driver directly. In this configuration, the driver sets back theconversion trigger pin to high as soon as it has read all the conversions.

• An external source is connected to the conversion trigger pin. In thecurrent implementation, it must be a PWM. In this configuration, the driverdoes not control directly the conversion trigger pin. Instead, it cancontrol the PWM’s frequency. This trigger is enabled only for iio-backend.

Reference voltage¶

2 possible reference voltage sources are supported:

• Internal reference (2.5V)

• External reference (2.5V)

The source is determined by the device tree. Ifrefin-supply is present,then the external reference is used, otherwise the internal reference is used.

Oversampling¶

This family supports oversampling to improve SNR.In software mode, the following ratios are available:1 (oversampling disabled)/2/4/8/16/32/64/128/256.

Unimplemented features¶

• 2/4/8 SDO lines

• CRC indication

• Calibration

IIO triggered buffer¶

This driver supports IIO triggered buffers, with a “built in” trigger, i.e thetrigger is allocated and linked by the driver, and a new conversion is triggeredas soon as the samples are transferred, and a timestamp channel is added to makeup for the potential jitter induced by the delays in the interrupt handling.

IIO backend buffer¶

When IIO backend is used, the trigger is not needed, and the sample rate isconsidered as stable. There is no timestamp channel. The communication isdelegated to an external logic, called a backend, and the backend’s driverhandles the buffer. When this mode is enabled, the driver cannot control theconversion pin, because the busy pin is bound to the backend.