Multi-tile Devices¶

Different vendors use the term “tile” a bit differently, but in the Intelworld, a ‘tile’ is pretty close to what most people would think of as beinga complete GPU. When multiple GPUs are placed behind a single PCI device,that’s what is referred to as a “multi-tile device.” In such cases, prettymuch all hardware is replicated per-tile, although certain responsibilitieslike PCI communication, reporting of interrupts to the OS, etc. are handledsolely by the “root tile.” A multi-tile platform takes care of tying thetiles together in a way such that interrupt notifications from remote tilesare forwarded to the root tile, the per-tile vram is combined into a singleaddress space, etc.

In contrast, a “GT” (which officially stands for “Graphics Technology”) isthe subset of a GPU/tile that is responsible for implementing graphicsand/or media operations. The GT is where a lot of the driver implementationhappens since it’s where the hardware engines, the execution units, and theGuC all reside.

Historically most Intel devices were single-tile devices that contained asingle GT. PVC is an example of an Intel platform built on a multi-tiledesign (i.e., multiple GPUs behind a single PCI device); each PVC tile onlyhas a single GT. In contrast, platforms like MTL that have separate chipsfor render and media IP are still only a single logical GPU, but thegraphics and media IP blocks are each exposed as a separate GT within thatsingle GPU. This is important from a software perspective because multi-GTplatforms like MTL only replicate a subset of the GPU hardware and behavedifferently than multi-tile platforms like PVC where nearly everything isreplicated.

Per-tile functionality (shared by all GTs within the tile):

• Complete 4MB MMIO space (containing SGunit/SoC registers, GTregisters, display registers, etc.)

• Global GTT

• VRAM (if discrete)

• Interrupt flows

• Migration context

• kernel batchbuffer pool

• Primary GT

• Media GT (if media version >= 13)

Per-GT functionality:

• GuC

• Hardware engines

• Programmable hardware units (subslices, EUs)

• GSI subset of registers (multiple copies of these registers residewithin the complete MMIO space provided by the tile, but at differentoffsets --- 0 for render, 0x380000 for media)

• Multicast register steering

• TLBs to cache page table translations

• Reset capability

• Low-level power management (e.g., C6)

• Clock frequency

• MOCS and PAT programming