Core Driver Infrastructure

GPU Hardware Structure

Each ASIC is a collection of hardware blocks. We refer to them as“IPs” (Intellectual Property blocks). Each IP encapsulates certainfunctionality. IPs are versioned and can also be mixed and matched.E.g., you might have two different ASICs that both have System DMA (SDMA) 5.x IPs.The driver is arranged by IPs. There are driver components to handlethe initialization and operation of each IP. There are also a bunchof smaller IPs that don’t really need much if any driver interaction.Those end up getting lumped into the common stuff in the soc files.The soc files (e.g., vi.c, soc15.c nv.c) contain code for aspects ofthe SoC itself rather than specific IPs. E.g., things like GPU resetsand register access functions are SoC dependent.

An APU contains more than just CPU and GPU, it also contains all ofthe platform stuff (audio, usb, gpio, etc.). Also, a lot ofcomponents are shared between the CPU, platform, and the GPU (e.g.,SMU, PSP, etc.). Specific components (CPU, GPU, etc.) usually havetheir interface to interact with those common components. For thingslike S0i3 there is a ton of coordination required across all thecomponents, but that is probably a bit beyond the scope of thissection.

With respect to the GPU, we have the following major IPs:

GMC (Graphics Memory Controller)

This was a dedicated IP on older pre-vega chips, but has sincebecome somewhat decentralized on vega and newer chips. They nowhave dedicated memory hubs for specific IPs or groups of IPs. Westill treat it as a single component in the driver however sincethe programming model is still pretty similar. This is how thedifferent IPs on the GPU get the memory (VRAM or system memory).It also provides the support for per process GPU virtual addressspaces.

IH (Interrupt Handler)

This is the interrupt controller on the GPU. All of the IPs feedtheir interrupts into this IP and it aggregates them into a set ofring buffers that the driver can parse to handle interrupts fromdifferent IPs.

PSP (Platform Security Processor)

This handles security policy for the SoC and executes trustedapplications, and validates and loads firmwares for other blocks.

SMU (System Management Unit)

This is the power management microcontroller. It manages the entireSoC. The driver interacts with it to control power managementfeatures like clocks, voltages, power rails, etc.

DCN (Display Controller Next)

This is the display controller. It handles the display hardware.It is described in more details inDisplay Core.

SDMA (System DMA)

This is a multi-purpose DMA engine. The kernel driver uses it forvarious things including paging and GPU page table updates. It’s alsoexposed to userspace for use by user mode drivers (OpenGL, Vulkan,etc.)

GC (Graphics and Compute)

This is the graphics and compute engine, i.e., the block thatencompasses the 3D pipeline and shader blocks. This is by far thelargest block on the GPU. The 3D pipeline has tons of sub-blocks. Inaddition to that, it also contains the CP microcontrollers (ME, PFP, CE,MEC) and the RLC microcontroller. It’s exposed to userspace for user modedrivers (OpenGL, Vulkan, OpenCL, etc.). More details inGraphics (GFX)and Compute.

VCN (Video Core Next)

This is the multi-media engine. It handles video and image encode anddecode. It’s exposed to userspace for user mode drivers (VA-API,OpenMAX, etc.)

It is important to note that these blocks can interact with each other. Thepicture below illustrates some of the components and their interconnection:

../../_images/amd_overview_block.svg

In the diagram, memory-related blocks are shown in green. Notice that specificIPs have a green square that represents a small hardware block named ‘hub’,which is responsible for interfacing with memory. All memory hubs are connectedin the UMCs, which in turn are connected to memory blocks. As a note,pre-vega devices have a dedicated block for the Graphic Memory Controller(GMC), which was replaced by UMC and hubs in new architectures. In the drivercode, you can identify this component by looking for the suffix hub, forexample: gfxhub, dchub, mmhub, vmhub, etc. Keep in mind that the component’sinteraction with the memory block may vary across architectures. For example,on Navi and newer, GC and SDMA are both attached to GCHUB; on pre-Navi, SDMAgoes through MMHUB; VCN, JPEG, and VPE go through MMHUB; DCN goes throughDCHUB.

There is some protection for certain memory elements, and the PSP plays anessential role in this area. When a specific firmware is loaded into memory,the PSP takes steps to ensure it has a valid signature. It also stores firmwareimages in a protected memory area named Trusted Memory Area (TMR), so the OS ordriver can’t corrupt them at runtime. Another use of PSP is to support TrustedApplications (TA), which are basically small applications that run on thetrusted processor and handles a trusted operation (e.g., HDCP). PSP is alsoused for encrypted memory for content protection via Trusted Memory Zone (TMZ).

Another critical IP is the SMU. It handles reset distribution, as well asclock, thermal, and power management for all IPs on the SoC. SMU also helps tobalance performance and power consumption.

GFX, Compute, and SDMA Overall Behavior

Note

For simplicity, whenever the term block is used in this section, itmeans GFX, Compute, and SDMA.

GFX, Compute and SDMA share a similar form of operation that can be abstractedto facilitate understanding of the behavior of these blocks. See the figurebelow illustrating the common components of these blocks:

../../_images/pipe_and_queue_abstraction.svg

In the central part of this figure, you can see two hardware elements, one calledPipes and another calledQueues; it is important to highlight that Queuesmust be associated with a Pipe and vice-versa. Every specific hardware IP may havea different number of Pipes and, in turn, a different number of Queues; forexample, GFX 11 has two Pipes and two Queues per Pipe for the GFX front end.

Pipe is the hardware that processes the instructions available in the Queues;in other words, it is a thread executing the operations inserted in the Queue.One crucial characteristic of Pipes is that they can only execute one Queue ata time; no matter if the hardware has multiple Queues in the Pipe, it only runsone Queue per Pipe.

Pipes have the mechanics of swapping between queues at the hardware level.Nonetheless, they only make use of Queues that are considered mapped. Pipes canswitch between queues based on any of the following inputs:

  1. Command Stream;

  2. Packet by Packet;

  3. Other hardware requests the change (e.g., MES).

Queues within Pipes are defined by the Hardware Queue Descriptors (HQD).Associated with the HQD concept, we have the Memory Queue Descriptor (MQD),which is responsible for storing information about the state of each of theavailable Queues in the memory. The state of a Queue contains information suchas the GPU virtual address of the queue itself, save areas, doorbell, etc. TheMQD also stores the HQD registers, which are vital for activating ordeactivating a given Queue. The scheduling firmware (e.g., MES) is responsiblefor loading HQDs from MQDs and vice versa.

The Queue-switching process can also happen with the firmware requesting thepreemption or unmapping of a Queue. The firmware waits for the HQD_ACTIVE bitto change to low before saving the state into the MQD. To make a differentQueue become active, the firmware copies the MQD state into the HQD registersand loads any additional state. Finally, it sets the HQD_ACTIVE bit to high toindicate that the queue is active. The Pipe will then execute work from activeQueues.

Driver Structure

In general, the driver has a list of all of the IPs on a particularSoC and for things like init/fini/suspend/resume, more or less justwalks the list and handles each IP.

Some useful constructs:

KIQ (Kernel Interface Queue)

This is a control queue used by the kernel driver to manage other gfxand compute queues on the GFX/compute engine. You can use it tomap/unmap additional queues, etc. This is replaced by MES onGFX 11 and newer hardware.

IB (Indirect Buffer)

A command buffer for a particular engine. Rather than writingcommands directly to the queue, you can write the commands into apiece of memory and then put a pointer to the memory into the queue.The hardware will then follow the pointer and execute the commands inthe memory, then returning to the rest of the commands in the ring.

Memory Domains

AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.Memory in this pool could be swapped out to disk if there is pressure.

AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into theGPU’s virtual address space via gart. Gart memory linearizes non-contiguouspages of system memory, allows GPU access system memory in a linearizedfashion.

AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memorycarved out by the BIOS.

AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share dataacross shader threads.

AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize theexecution of all the waves on a device.

AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute enginesfor appending data.

AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region forsignalling user mode queues.

Buffer Objects

This defines the interfaces to operate on anamdgpu_bo buffer object whichrepresents memory used by driver (VRAM, system memory, etc.). The driverprovides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfacesto create/destroy/set buffer object which are then managed by the kernel TTMmemory manager.The interfaces are also used internally by kernel clients, including gfx,uvd, etc. for kernel managed allocations used by the GPU.

boolamdgpu_bo_is_amdgpu_bo(structttm_buffer_object*bo)

check if the buffer object is anamdgpu_bo

Parameters

structttm_buffer_object*bo

buffer object to be checked

Description

Uses destroy function associated with the object to determine if this isanamdgpu_bo.

Return

true if the object belongs toamdgpu_bo, false if not.

voidamdgpu_bo_placement_from_domain(structamdgpu_bo*abo,u32domain)

set buffer’s placement

Parameters

structamdgpu_bo*abo

amdgpu_bo buffer object whose placement is to be set

u32domain

requested domain

Description

Sets buffer’s placement according to requested domain and the buffer’sflags.

intamdgpu_bo_create_reserved(structamdgpu_device*adev,unsignedlongsize,intalign,u32domain,structamdgpu_bo**bo_ptr,u64*gpu_addr,void**cpu_addr)

create reserved BO for kernel use

Parameters

structamdgpu_device*adev

amdgpu device object

unsignedlongsize

size for the new BO

intalign

alignment for the new BO

u32domain

where to place it

structamdgpu_bo**bo_ptr

used to initialize BOs in structures

u64*gpu_addr

GPU addr of the pinned BO

void**cpu_addr

optional CPU address mapping

Description

Allocates and pins a BO for kernel internal use, and returns it stillreserved.

Note

For bo_ptr new BO is only created if bo_ptr points to NULL.

Return

0 on success, negative error code otherwise.

intamdgpu_bo_create_kernel(structamdgpu_device*adev,unsignedlongsize,intalign,u32domain,structamdgpu_bo**bo_ptr,u64*gpu_addr,void**cpu_addr)

create BO for kernel use

Parameters

structamdgpu_device*adev

amdgpu device object

unsignedlongsize

size for the new BO

intalign

alignment for the new BO

u32domain

where to place it

structamdgpu_bo**bo_ptr

used to initialize BOs in structures

u64*gpu_addr

GPU addr of the pinned BO

void**cpu_addr

optional CPU address mapping

Description

Allocates and pins a BO for kernel internal use.

This function is exported to allow the V4L2 isp deviceexternal to drm device to create and access the kernel BO.

Note

For bo_ptr new BO is only created if bo_ptr points to NULL.

Return

0 on success, negative error code otherwise.

intamdgpu_bo_create_isp_user(structamdgpu_device*adev,structdma_buf*dma_buf,u32domain,structamdgpu_bo**bo,u64*gpu_addr)

create user BO for isp

Parameters

structamdgpu_device*adev

amdgpu device object

structdma_buf*dma_buf

DMABUF handle for isp buffer

u32domain

where to place it

structamdgpu_bo**bo

used to initialize BOs in structures

u64*gpu_addr

GPU addr of the pinned BO

Description

Imports isp DMABUF to allocate and pin a user BO for isp internal use. It doesGART alloc to generate gpu_addr for BO to make it accessible through theGART aperture for ISP HW.

This function is exported to allow the V4L2 isp device external to drm deviceto create and access the isp user BO.

Return

0 on success, negative error code otherwise.

intamdgpu_bo_create_kernel_at(structamdgpu_device*adev,uint64_toffset,uint64_tsize,structamdgpu_bo**bo_ptr,void**cpu_addr)

create BO for kernel use at specific location

Parameters

structamdgpu_device*adev

amdgpu device object

uint64_toffset

offset of the BO

uint64_tsize

size of the BO

structamdgpu_bo**bo_ptr

used to initialize BOs in structures

void**cpu_addr

optional CPU address mapping

Description

Creates a kernel BO at a specific offset in VRAM.

Return

0 on success, negative error code otherwise.

voidamdgpu_bo_free_kernel(structamdgpu_bo**bo,u64*gpu_addr,void**cpu_addr)

free BO for kernel use

Parameters

structamdgpu_bo**bo

amdgpu BO to free

u64*gpu_addr

pointer to where the BO’s GPU memory space address was stored

void**cpu_addr

pointer to where the BO’s CPU memory space address was stored

Description

unmaps and unpin a BO for kernel internal use.

This function is exported to allow the V4L2 isp deviceexternal to drm device to free the kernel BO.

voidamdgpu_bo_free_isp_user(structamdgpu_bo*bo)

free BO for isp use

Parameters

structamdgpu_bo*bo

amdgpu isp user BO to free

Description

unpin and unref BO for isp internal use.

This function is exported to allow the V4L2 isp deviceexternal to drm device to free the isp user BO.

intamdgpu_bo_create(structamdgpu_device*adev,structamdgpu_bo_param*bp,structamdgpu_bo**bo_ptr)

create anamdgpu_bo buffer object

Parameters

structamdgpu_device*adev

amdgpu device object

structamdgpu_bo_param*bp

parameters to be used for the buffer object

structamdgpu_bo**bo_ptr

pointer to the buffer object pointer

Description

Creates anamdgpu_bo buffer object.

Return

0 for success or a negative error code on failure.

intamdgpu_bo_create_user(structamdgpu_device*adev,structamdgpu_bo_param*bp,structamdgpu_bo_user**ubo_ptr)

create anamdgpu_bo_user buffer object

Parameters

structamdgpu_device*adev

amdgpu device object

structamdgpu_bo_param*bp

parameters to be used for the buffer object

structamdgpu_bo_user**ubo_ptr

pointer to the buffer object pointer

Description

Create a BO to be used by user application;

Return

0 for success or a negative error code on failure.

intamdgpu_bo_create_vm(structamdgpu_device*adev,structamdgpu_bo_param*bp,structamdgpu_bo_vm**vmbo_ptr)

create anamdgpu_bo_vm buffer object

Parameters

structamdgpu_device*adev

amdgpu device object

structamdgpu_bo_param*bp

parameters to be used for the buffer object

structamdgpu_bo_vm**vmbo_ptr

pointer to the buffer object pointer

Description

Create a BO to be for GPUVM.

Return

0 for success or a negative error code on failure.

intamdgpu_bo_kmap(structamdgpu_bo*bo,void**ptr)

map anamdgpu_bo buffer object

Parameters

structamdgpu_bo*bo

amdgpu_bo buffer object to be mapped

void**ptr

kernel virtual address to be returned

Description

Callsttm_bo_kmap() to set up the kernel virtual mapping; callsamdgpu_bo_kptr() to get the kernel virtual address.

Return

0 for success or a negative error code on failure.

void*amdgpu_bo_kptr(structamdgpu_bo*bo)

returns a kernel virtual address of the buffer object

Parameters

structamdgpu_bo*bo

amdgpu_bo buffer object

Description

Callsttm_kmap_obj_virtual() to get the kernel virtual address

Return

the virtual address of a buffer object area.

voidamdgpu_bo_kunmap(structamdgpu_bo*bo)

unmap anamdgpu_bo buffer object

Parameters

structamdgpu_bo*bo

amdgpu_bo buffer object to be unmapped

Description

Unmaps a kernel map set up byamdgpu_bo_kmap().

structamdgpu_bo*amdgpu_bo_ref(structamdgpu_bo*bo)

reference anamdgpu_bo buffer object

Parameters

structamdgpu_bo*bo

amdgpu_bo buffer object

Description

References the containedttm_buffer_object.

Return

a refcounted pointer to theamdgpu_bo buffer object.

voidamdgpu_bo_unref(structamdgpu_bo**bo)

unreference anamdgpu_bo buffer object

Parameters

structamdgpu_bo**bo

amdgpu_bo buffer object

Description

Unreferences the containedttm_buffer_object and clear the pointer

intamdgpu_bo_pin(structamdgpu_bo*bo,u32domain)

pin anamdgpu_bo buffer object

Parameters

structamdgpu_bo*bo

amdgpu_bo buffer object to be pinned

u32domain

domain to be pinned to

Description

Pins the buffer object according to requested domain. If the memory isunbound gart memory, binds the pages into gart table. Adjusts pin_count andpin_size accordingly.

Pinning means to lock pages in memory along with keeping them at a fixedoffset. It is required when a buffer can not be moved, for example, whena display buffer is being scanned out.

Return

0 for success or a negative error code on failure.

voidamdgpu_bo_unpin(structamdgpu_bo*bo)

unpin anamdgpu_bo buffer object

Parameters

structamdgpu_bo*bo

amdgpu_bo buffer object to be unpinned

Description

Decreases the pin_count, and clears the flags if pin_count reaches 0.Changes placement and pin size accordingly.

Return

0 for success or a negative error code on failure.

intamdgpu_bo_init(structamdgpu_device*adev)

initialize memory manager

Parameters

structamdgpu_device*adev

amdgpu device object

Description

Callsamdgpu_ttm_init() to initialize amdgpu memory manager.

Return

0 for success or a negative error code on failure.

voidamdgpu_bo_fini(structamdgpu_device*adev)

tear down memory manager

Parameters

structamdgpu_device*adev

amdgpu device object

Description

Reversesamdgpu_bo_init() to tear down memory manager.

intamdgpu_bo_set_tiling_flags(structamdgpu_bo*bo,u64tiling_flags)

set tiling flags

Parameters

structamdgpu_bo*bo

amdgpu_bo buffer object

u64tiling_flags

new flags

Description

Sets buffer object’s tiling flags with the new one. Used by GEM ioctl orkernel driver to set the tiling flags on a buffer.

Return

0 for success or a negative error code on failure.

voidamdgpu_bo_get_tiling_flags(structamdgpu_bo*bo,u64*tiling_flags)

get tiling flags

Parameters

structamdgpu_bo*bo

amdgpu_bo buffer object

u64*tiling_flags

returned flags

Description

Gets buffer object’s tiling flags. Used by GEM ioctl or kernel driver toset the tiling flags on a buffer.

intamdgpu_bo_set_metadata(structamdgpu_bo*bo,void*metadata,u32metadata_size,uint64_tflags)

set metadata

Parameters

structamdgpu_bo*bo

amdgpu_bo buffer object

void*metadata

new metadata

u32metadata_size

size of the new metadata

uint64_tflags

flags of the new metadata

Description

Sets buffer object’s metadata, its size and flags.Used via GEM ioctl.

Return

0 for success or a negative error code on failure.

intamdgpu_bo_get_metadata(structamdgpu_bo*bo,void*buffer,size_tbuffer_size,uint32_t*metadata_size,uint64_t*flags)

get metadata

Parameters

structamdgpu_bo*bo

amdgpu_bo buffer object

void*buffer

returned metadata

size_tbuffer_size

size of the buffer

uint32_t*metadata_size

size of the returned metadata

uint64_t*flags

flags of the returned metadata

Description

Gets buffer object’s metadata, its size and flags. buffer_size shall not beless than metadata_size.Used via GEM ioctl.

Return

0 for success or a negative error code on failure.

voidamdgpu_bo_move_notify(structttm_buffer_object*bo,boolevict,structttm_resource*new_mem)

notification about a memory move

Parameters

structttm_buffer_object*bo

pointer to a buffer object

boolevict

if this move is evicting the buffer from the graphics address space

structttm_resource*new_mem

new resource for backing the BO

Description

Marks the correspondingamdgpu_bo buffer object as invalid, also performsbookkeeping.TTM driver callback which is called when ttm moves a buffer.

voidamdgpu_bo_release_notify(structttm_buffer_object*bo)

notification about a BO being released

Parameters

structttm_buffer_object*bo

pointer to a buffer object

Description

Wipes VRAM buffers whose contents should not be leaked before thememory is released.

vm_fault_tamdgpu_bo_fault_reserve_notify(structttm_buffer_object*bo)

notification about a memory fault

Parameters

structttm_buffer_object*bo

pointer to a buffer object

Description

Notifies the driver we are taking a fault on this BO and have reserved it,also performs bookkeeping.TTM driver callback for dealing with vm faults.

Return

0 for success or a negative error code on failure.

voidamdgpu_bo_fence(structamdgpu_bo*bo,structdma_fence*fence,boolshared)

add fence to buffer object

Parameters

structamdgpu_bo*bo

buffer object in question

structdma_fence*fence

fence to add

boolshared

true if fence should be added shared

intamdgpu_bo_sync_wait_resv(structamdgpu_device*adev,structdma_resv*resv,enumamdgpu_sync_modesync_mode,void*owner,boolintr)

Wait for BO reservation fences

Parameters

structamdgpu_device*adev

amdgpu device pointer

structdma_resv*resv

reservation object to sync to

enumamdgpu_sync_modesync_mode

synchronization mode

void*owner

fence owner

boolintr

Whether the wait is interruptible

Description

Extract the fences from the reservation object and waits for them to finish.

Return

0 on success, errno otherwise.

intamdgpu_bo_sync_wait(structamdgpu_bo*bo,void*owner,boolintr)

Wrapper for amdgpu_bo_sync_wait_resv

Parameters

structamdgpu_bo*bo

buffer object to wait for

void*owner

fence owner

boolintr

Whether the wait is interruptible

Description

Wrapper to wait for fences in a BO.

Return

0 on success, errno otherwise.

u64amdgpu_bo_gpu_offset(structamdgpu_bo*bo)

return GPU offset of bo

Parameters

structamdgpu_bo*bo

amdgpu object for which we query the offset

Note

object should either be pinned or reserved when calling thisfunction, it might be useful to add check for this for debugging.

Return

current GPU offset of the object.

u64amdgpu_bo_fb_aper_addr(structamdgpu_bo*bo)

return FB aperture GPU offset of the VRAM bo

Parameters

structamdgpu_bo*bo

amdgpu VRAM buffer object for which we query the offset

Return

current FB aperture GPU offset of the object.

u64amdgpu_bo_gpu_offset_no_check(structamdgpu_bo*bo)

return GPU offset of bo

Parameters

structamdgpu_bo*bo

amdgpu object for which we query the offset

Return

current GPU offset of the object without raising warnings.

uint32_tamdgpu_bo_mem_stats_placement(structamdgpu_bo*bo)

bo placement for memory accounting

Parameters

structamdgpu_bo*bo

the buffer object we should look at

Description

BO can have multiple preferred placements, to avoid double counting we wantto file it under a single placement for memory stats.Luckily, if we take the highest set bit in preferred_domains the result isquite sensible.

Return

Which of the placements should the BO be accounted under.

uint32_tamdgpu_bo_get_preferred_domain(structamdgpu_device*adev,uint32_tdomain)

get preferred domain

Parameters

structamdgpu_device*adev

amdgpu device object

uint32_tdomain

allowedmemory domains

Return

Which of the allowed domains is preferred for allocating the BO.

u64amdgpu_bo_print_info(intid,structamdgpu_bo*bo,structseq_file*m)

print BO info in debugfs file

Parameters

intid

Index or Id of the BO

structamdgpu_bo*bo

Requested BO for printing info

structseq_file*m

debugfs file

Description

Print BO information in debugfs file

Return

Size of the BO in bytes.

PRIME Buffer Sharing

The following callback implementations are used forsharing GEM bufferobjects between different devices via PRIME.

structamdgpu_device*dma_buf_attach_adev(structdma_buf_attachment*attach)

Helper to get adev of an attachment

Parameters

structdma_buf_attachment*attach

attachment

Return

Astructamdgpu_device * if the attaching device is an amdgpu device orpartition, NULL otherwise.

intamdgpu_dma_buf_attach(structdma_buf*dmabuf,structdma_buf_attachment*attach)

dma_buf_ops.attach implementation

Parameters

structdma_buf*dmabuf

DMA-buf where we attach to

structdma_buf_attachment*attach

attachment to add

Description

Add the attachment as user to the exported DMA-buf.

intamdgpu_dma_buf_pin(structdma_buf_attachment*attach)

dma_buf_ops.pin implementation

Parameters

structdma_buf_attachment*attach

attachment to pin down

Description

Pin the BO which is backing the DMA-buf so that it can’t move any more.

voidamdgpu_dma_buf_unpin(structdma_buf_attachment*attach)

dma_buf_ops.unpin implementation

Parameters

structdma_buf_attachment*attach

attachment to unpin

Description

Unpin a previously pinned BO to make it movable again.

structsg_table*amdgpu_dma_buf_map(structdma_buf_attachment*attach,enumdma_data_directiondir)

dma_buf_ops.map_dma_buf implementation

Parameters

structdma_buf_attachment*attach

DMA-buf attachment

enumdma_data_directiondir

DMA direction

Description

Makes sure that the shared DMA buffer can be accessed by the target device.For now, simply pins it to the GTT domain, where it should be accessible byall DMA devices.

Return

sg_table filled with the DMA addresses to use or ERR_PRT with negative errorcode.

voidamdgpu_dma_buf_unmap(structdma_buf_attachment*attach,structsg_table*sgt,enumdma_data_directiondir)

dma_buf_ops.unmap_dma_buf implementation

Parameters

structdma_buf_attachment*attach

DMA-buf attachment

structsg_table*sgt

sg_table to unmap

enumdma_data_directiondir

DMA direction

Description

This is called when a shared DMA buffer no longer needs to be accessible byanother device. For now, simply unpins the buffer from GTT.

intamdgpu_dma_buf_begin_cpu_access(structdma_buf*dma_buf,enumdma_data_directiondirection)

dma_buf_ops.begin_cpu_access implementation

Parameters

structdma_buf*dma_buf

Shared DMA buffer

enumdma_data_directiondirection

Direction of DMA transfer

Description

This is called before CPU access to the shared DMA buffer’s memory. If it’sa read access, the buffer is moved to the GTT domain if possible, for optimalCPU read performance.

Return

0 on success or a negative error code on failure.

structdma_buf*amdgpu_gem_prime_export(structdrm_gem_object*gobj,intflags)

drm_driver.gem_prime_export implementation

Parameters

structdrm_gem_object*gobj

GEM BO

intflags

Flags such as DRM_CLOEXEC and DRM_RDWR.

Description

The main work is done by thedrm_gem_prime_export helper.

Return

Shared DMA buffer representing the GEM BO from the given device.

structdrm_gem_object*amdgpu_dma_buf_create_obj(structdrm_device*dev,structdma_buf*dma_buf)

create BO for DMA-buf import

Parameters

structdrm_device*dev

DRM device

structdma_buf*dma_buf

DMA-buf

Description

Creates an empty SG BO for DMA-buf import.

Return

A new GEM BO of the given DRM device, representing the memorydescribed by the given DMA-buf attachment and scatter/gather table.

voidamdgpu_dma_buf_move_notify(structdma_buf_attachment*attach)

attach.invalidate_mappings implementation

Parameters

structdma_buf_attachment*attach

the DMA-buf attachment

Description

Invalidate the DMA-buf attachment, making sure that the we re-create themapping before the next use.

structdrm_gem_object*amdgpu_gem_prime_import(structdrm_device*dev,structdma_buf*dma_buf)

drm_driver.gem_prime_import implementation

Parameters

structdrm_device*dev

DRM device

structdma_buf*dma_buf

Shared DMA buffer

Description

Import a dma_buf into a the driver and potentially create a new GEM object.

Return

GEM BO representing the shared DMA buffer for the given device.

boolamdgpu_dmabuf_is_xgmi_accessible(structamdgpu_device*adev,structamdgpu_bo*bo)

Check if xgmi available for P2P transfer

Parameters

structamdgpu_device*adev

amdgpu_device pointer of the importer

structamdgpu_bo*bo

amdgpu buffer object

Return

True if dmabuf accessible over xgmi, false otherwise.

MMU Notifier

For coherent userptr handling registers an MMU notifier to inform the driverabout updates on the page tables of a process.

When somebody tries to invalidate the page tables we block the update untilall operations on the pages in question are completed, then those pages aremarked as accessed and also dirty if it wasn’t a read only access.

New command submissions using the userptrs in question are delayed until allpage table invalidation are completed and we once more see a coherent processaddress space.

boolamdgpu_hmm_invalidate_gfx(structmmu_interval_notifier*mni,conststructmmu_notifier_range*range,unsignedlongcur_seq)

callback to notify about mm change

Parameters

structmmu_interval_notifier*mni

the range (mm) is about to update

conststructmmu_notifier_range*range

details on the invalidation

unsignedlongcur_seq

Value to pass tommu_interval_set_seq()

Description

Block for operations on BOs to finish and mark pages as accessed andpotentially dirty.

boolamdgpu_hmm_invalidate_hsa(structmmu_interval_notifier*mni,conststructmmu_notifier_range*range,unsignedlongcur_seq)

callback to notify about mm change

Parameters

structmmu_interval_notifier*mni

the range (mm) is about to update

conststructmmu_notifier_range*range

details on the invalidation

unsignedlongcur_seq

Value to pass tommu_interval_set_seq()

Description

We temporarily evict the BO attached to this range. This necessitatesevicting all user-mode queues of the process.

intamdgpu_hmm_register(structamdgpu_bo*bo,unsignedlongaddr)

register a BO for notifier updates

Parameters

structamdgpu_bo*bo

amdgpu buffer object

unsignedlongaddr

userptr addr we should monitor

Description

Registers a mmu_notifier for the given BO at the specified address.Returns 0 on success, -ERRNO if anything goes wrong.

voidamdgpu_hmm_unregister(structamdgpu_bo*bo)

unregister a BO for notifier updates

Parameters

structamdgpu_bo*bo

amdgpu buffer object

Description

Remove any registration of mmu notifier updates from the buffer object.

boolamdgpu_hmm_range_valid(structamdgpu_hmm_range*range)

check if an HMM range is still valid

Parameters

structamdgpu_hmm_range*range

pointer to thestructamdgpu_hmm_range to validate

Description

Determines whether the given HMM rangerange is still valid bychecking for invalidations via the MMU notifier sequence. This istypically used to verify that the range has not been invalidatedby concurrent address space updates before it is accessed.

Return

  • true ifrange is valid and can be used safely

  • false ifrange is NULL or has been invalidated

structamdgpu_hmm_range*amdgpu_hmm_range_alloc(structamdgpu_bo*bo)

allocate and initialize an AMDGPU HMM range

Parameters

structamdgpu_bo*bo

optional buffer object to associate with this HMM range

Description

Allocates memory for amdgpu_hmm_range and associates it with thebo passed.The reference count of thebo is incremented.

Return

Pointer to a newly allocatedstructamdgpu_hmm_range on success,or NULL if memory allocation fails.

voidamdgpu_hmm_range_free(structamdgpu_hmm_range*range)

release an AMDGPU HMM range

Parameters

structamdgpu_hmm_range*range

pointer to the range object to free

Description

Releases all resources held byrange, including the associatedhmm_pfns and the dropping reference of associated bo if any.

Return

void

AMDGPU Virtual Memory

GPUVM is the MMU functionality provided on the GPU.GPUVM is similar to the legacy GART on older asics, howeverrather than there being a single global GART tablefor the entire GPU, there can be multiple GPUVM page tables activeat any given time. The GPUVM page tables can contain a mixVRAM pages and system pages (both memory and MMIO) and system pagescan be mapped as snooped (cached system pages) or unsnooped(uncached system pages).

Each active GPUVM has an ID associated with it and there is a page tablelinked with each VMID. When executing a command buffer,the kernel tells the engine what VMID to use for that commandbuffer. VMIDs are allocated dynamically as commands are submitted.The userspace drivers maintain their own address space and the kernelsets up their pages tables accordingly when they submit theircommand buffers and a VMID is assigned.The hardware supports up to 16 active GPUVMs at any given time.

Each GPUVM is represented by a 1-2 or 1-5 level page table, dependingon the ASIC family. GPUVM supports RWX attributes on each page as wellas other features such as encryption and caching attributes.

VMID 0 is special. It is the GPUVM used for the kernel driver. Inaddition to an aperture managed by a page table, VMID 0 also hasseveral other apertures. There is an aperture for direct access to VRAMand there is a legacy AGP aperture which just forwards accesses directlyto the matching system physical addresses (or IOVAs when an IOMMU ispresent). These apertures provide direct access to these memories withoutincurring the overhead of a page table. VMID 0 is used by the kerneldriver for tasks like memory management.

GPU clients (i.e., engines on the GPU) use GPUVM VMIDs to access memory.For user applications, each application can have their own unique GPUVMaddress space. The application manages the address space and the kerneldriver manages the GPUVM page tables for each process. If an GPU clientaccesses an invalid page, it will generate a GPU page fault, similar toaccessing an invalid page on a CPU.

structamdgpu_prt_cb

Helper to disable partial resident texture feature from a fence callback

Definition:

struct amdgpu_prt_cb {    struct amdgpu_device *adev;    struct dma_fence_cb cb;};

Members

adev

amdgpu device

cb

callback

structamdgpu_vm_tlb_seq_struct

Helper to increment the TLB flush sequence

Definition:

struct amdgpu_vm_tlb_seq_struct {    struct amdgpu_vm *vm;    struct dma_fence_cb cb;};

Members

vm

pointer to the amdgpu_vm structure to set the fence sequence on

cb

callback

voidamdgpu_vm_assert_locked(structamdgpu_vm*vm)

check if VM is correctly locked

Parameters

structamdgpu_vm*vm

the VM which schould be tested

Description

Asserts that the VM root PD is locked.

voidamdgpu_vm_bo_evicted(structamdgpu_vm_bo_base*vm_bo)

vm_bo is evicted

Parameters

structamdgpu_vm_bo_base*vm_bo

vm_bo which is evicted

Description

State for PDs/PTs and per VM BOs which are not at the location they shouldbe.

voidamdgpu_vm_bo_moved(structamdgpu_vm_bo_base*vm_bo)

vm_bo is moved

Parameters

structamdgpu_vm_bo_base*vm_bo

vm_bo which is moved

Description

State for per VM BOs which are moved, but that change is not yet reflectedin the page tables.

voidamdgpu_vm_bo_idle(structamdgpu_vm_bo_base*vm_bo)

vm_bo is idle

Parameters

structamdgpu_vm_bo_base*vm_bo

vm_bo which is now idle

Description

State for PDs/PTs and per VM BOs which have gone through the state machineand are now idle.

voidamdgpu_vm_bo_invalidated(structamdgpu_vm_bo_base*vm_bo)

vm_bo is invalidated

Parameters

structamdgpu_vm_bo_base*vm_bo

vm_bo which is now invalidated

Description

State for normal BOs which are invalidated and that change not yet reflectedin the PTs.

voidamdgpu_vm_bo_evicted_user(structamdgpu_vm_bo_base*vm_bo)

vm_bo is evicted

Parameters

structamdgpu_vm_bo_base*vm_bo

vm_bo which is evicted

Description

State for BOs used by user mode queues which are not at the location theyshould be.

voidamdgpu_vm_bo_relocated(structamdgpu_vm_bo_base*vm_bo)

vm_bo is reloacted

Parameters

structamdgpu_vm_bo_base*vm_bo

vm_bo which is relocated

Description

State for PDs/PTs which needs to update their parent PD.For the root PD, just move to idle state.

voidamdgpu_vm_bo_done(structamdgpu_vm_bo_base*vm_bo)

vm_bo is done

Parameters

structamdgpu_vm_bo_base*vm_bo

vm_bo which is now done

Description

State for normal BOs which are invalidated and that change has been updatedin the PTs.

voidamdgpu_vm_bo_reset_state_machine(structamdgpu_vm*vm)

reset the vm_bo state machine

Parameters

structamdgpu_vm*vm

the VM which state machine to reset

Description

Move all vm_bo object in the VM into a state where they will be updatedagain during validation.

voidamdgpu_vm_update_shared(structamdgpu_vm_bo_base*base)

helper to update shared memory stat

Parameters

structamdgpu_vm_bo_base*base

base structure for tracking BO usage in a VM

Description

Takes the vm status_lock and updates the shared memory stat. If the basicstat changed (e.g. buffer was moved) amdgpu_vm_update_stats need to be calledas well.

voidamdgpu_vm_bo_update_shared(structamdgpu_bo*bo)

callback when bo gets shared/unshared

Parameters

structamdgpu_bo*bo

amdgpu buffer object

Description

Update the per VM stats for all the vm if needed from private to shared orvice versa.

voidamdgpu_vm_update_stats_locked(structamdgpu_vm_bo_base*base,structttm_resource*res,intsign)

helper to update normal memory stat

Parameters

structamdgpu_vm_bo_base*base

base structure for tracking BO usage in a VM

structttm_resource*res

the ttm_resource to use for the purpose of accounting, may or may notbe bo->tbo.resource

intsign

if we should add (+1) or subtract (-1) from the stat

Description

Caller need to have the vm status_lock held. Useful for when multiple updateneed to happen at the same time.

voidamdgpu_vm_update_stats(structamdgpu_vm_bo_base*base,structttm_resource*res,intsign)

helper to update normal memory stat

Parameters

structamdgpu_vm_bo_base*base

base structure for tracking BO usage in a VM

structttm_resource*res

the ttm_resource to use for the purpose of accounting, may or may notbe bo->tbo.resource

intsign

if we should add (+1) or subtract (-1) from the stat

Description

Updates the basic memory stat when bo is added/deleted/moved.

voidamdgpu_vm_bo_base_init(structamdgpu_vm_bo_base*base,structamdgpu_vm*vm,structamdgpu_bo*bo)

Adds bo to the list of bos associated with the vm

Parameters

structamdgpu_vm_bo_base*base

base structure for tracking BO usage in a VM

structamdgpu_vm*vm

vm to which bo is to be added

structamdgpu_bo*bo

amdgpu buffer object

Description

Initialize a bo_va_base structure and add it to the appropriate lists

intamdgpu_vm_lock_pd(structamdgpu_vm*vm,structdrm_exec*exec,unsignedintnum_fences)

lock PD in drm_exec

Parameters

structamdgpu_vm*vm

vm providing the BOs

structdrm_exec*exec

drm execution context

unsignedintnum_fences

number of extra fences to reserve

Description

Lock the VM root PD in the DRM execution context.

intamdgpu_vm_lock_done_list(structamdgpu_vm*vm,structdrm_exec*exec,unsignedintnum_fences)

lock all BOs on the done list

Parameters

structamdgpu_vm*vm

vm providing the BOs

structdrm_exec*exec

drm execution context

unsignedintnum_fences

number of extra fences to reserve

Description

Lock the BOs on the done list in the DRM execution context.

voidamdgpu_vm_move_to_lru_tail(structamdgpu_device*adev,structamdgpu_vm*vm)

move all BOs to the end of LRU

Parameters

structamdgpu_device*adev

amdgpu device pointer

structamdgpu_vm*vm

vm providing the BOs

Description

Move all BOs to the end of LRU and remember their positions to put themtogether.

uint64_tamdgpu_vm_generation(structamdgpu_device*adev,structamdgpu_vm*vm)

return the page table re-generation counter

Parameters

structamdgpu_device*adev

the amdgpu_device

structamdgpu_vm*vm

optional VM to check, might be NULL

Description

Returns a page table re-generation token to allow checking if submissionsare still valid to use this VM. The VM parameter might be NULL in which casejust the VRAM lost counter will be used.

intamdgpu_vm_validate(structamdgpu_device*adev,structamdgpu_vm*vm,structww_acquire_ctx*ticket,int(*validate)(void*p,structamdgpu_bo*bo),void*param)

validate evicted BOs tracked in the VM

Parameters

structamdgpu_device*adev

amdgpu device pointer

structamdgpu_vm*vm

vm providing the BOs

structww_acquire_ctx*ticket

optional reservation ticket used to reserve the VM

int(*validate)(void*p,structamdgpu_bo*bo)

callback to do the validation

void*param

parameter for the validation callback

Description

Validate the page table BOs and per-VM BOs on command submission ifnecessary. If a ticket is given, also try to validate evicted user queueBOs. They must already be reserved with the given ticket.

Return

Validation result.

boolamdgpu_vm_ready(structamdgpu_vm*vm)

check VM is ready for updates

Parameters

structamdgpu_vm*vm

VM to check

Description

Check if all VM PDs/PTs are ready for updates

Return

True if VM is not evicting and all VM entities are not stopped

voidamdgpu_vm_check_compute_bug(structamdgpu_device*adev)

check whether asic has compute vm bug

Parameters

structamdgpu_device*adev

amdgpu_device pointer

boolamdgpu_vm_need_pipeline_sync(structamdgpu_ring*ring,structamdgpu_job*job)

Check if pipe sync is needed for job.

Parameters

structamdgpu_ring*ring

ring on which the job will be submitted

structamdgpu_job*job

job to submit

Return

True if sync is needed.

intamdgpu_vm_flush(structamdgpu_ring*ring,structamdgpu_job*job,boolneed_pipe_sync)

hardware flush the vm

Parameters

structamdgpu_ring*ring

ring to use for flush

structamdgpu_job*job

related job

boolneed_pipe_sync

is pipe sync needed

Description

Emit a VM flush when it is necessary.

Return

0 on success, errno otherwise.

structamdgpu_bo_va*amdgpu_vm_bo_find(structamdgpu_vm*vm,structamdgpu_bo*bo)

find the bo_va for a specific vm & bo

Parameters

structamdgpu_vm*vm

requested vm

structamdgpu_bo*bo

requested buffer object

Description

Findbo inside the requested vm.Search inside thebos vm list for the requested vmReturns the found bo_va or NULL if none is found

Object has to be reserved!

Return

Found bo_va or NULL.

uint64_tamdgpu_vm_map_gart(constdma_addr_t*pages_addr,uint64_taddr)

Resolve gart mapping of addr

Parameters

constdma_addr_t*pages_addr

optional DMA address to use for lookup

uint64_taddr

the unmapped addr

Description

Look up the physical address of the page that the pte resolvesto.

Return

The pointer for the page table entry.

intamdgpu_vm_update_pdes(structamdgpu_device*adev,structamdgpu_vm*vm,boolimmediate)

make sure that all directories are valid

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structamdgpu_vm*vm

requested vm

boolimmediate

submit immediately to the paging queue

Description

Makes sure all directories are up to date.

Return

0 for success, error for failure.

voidamdgpu_vm_tlb_seq_cb(structdma_fence*fence,structdma_fence_cb*cb)

make sure to increment tlb sequence

Parameters

structdma_fence*fence

unused

structdma_fence_cb*cb

the callback structure

Description

Increments the tlb sequence to make sure that future CS execute a VM flush.

voidamdgpu_vm_tlb_flush(structamdgpu_vm_update_params*params,structdma_fence**fence,structamdgpu_vm_tlb_seq_struct*tlb_cb)

prepare TLB flush

Parameters

structamdgpu_vm_update_params*params

parameters for update

structdma_fence**fence

input fence to sync TLB flush with

structamdgpu_vm_tlb_seq_struct*tlb_cb

the callback structure

Description

Increments the tlb sequence to make sure that future CS execute a VM flush.

intamdgpu_vm_update_range(structamdgpu_device*adev,structamdgpu_vm*vm,boolimmediate,boolunlocked,boolflush_tlb,boolallow_override,structamdgpu_sync*sync,uint64_tstart,uint64_tlast,uint64_tflags,uint64_toffset,uint64_tvram_base,structttm_resource*res,dma_addr_t*pages_addr,structdma_fence**fence)

update a range in the vm page table

Parameters

structamdgpu_device*adev

amdgpu_device pointer to use for commands

structamdgpu_vm*vm

the VM to update the range

boolimmediate

immediate submission in a page fault

boolunlocked

unlocked invalidation during MM callback

boolflush_tlb

trigger tlb invalidation after update completed

boolallow_override

change MTYPE for local NUMA nodes

structamdgpu_sync*sync

fences we need to sync to

uint64_tstart

start of mapped range

uint64_tlast

last mapped entry

uint64_tflags

flags for the entries

uint64_toffset

offset into nodes and pages_addr

uint64_tvram_base

base for vram mappings

structttm_resource*res

ttm_resource to map

dma_addr_t*pages_addr

DMA addresses to use for mapping

structdma_fence**fence

optional resulting fence

Description

Fill in the page table entries betweenstart andlast.

Return

0 for success, negative erro code for failure.

intamdgpu_vm_bo_update(structamdgpu_device*adev,structamdgpu_bo_va*bo_va,boolclear)

update all BO mappings in the vm page table

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structamdgpu_bo_va*bo_va

requested BO and VM object

boolclear

if true clear the entries

Description

Fill in the page table entries forbo_va.

Return

0 for success, -EINVAL for failure.

voidamdgpu_vm_update_prt_state(structamdgpu_device*adev)

update the global PRT state

Parameters

structamdgpu_device*adev

amdgpu_device pointer

voidamdgpu_vm_prt_get(structamdgpu_device*adev)

add a PRT user

Parameters

structamdgpu_device*adev

amdgpu_device pointer

voidamdgpu_vm_prt_put(structamdgpu_device*adev)

drop a PRT user

Parameters

structamdgpu_device*adev

amdgpu_device pointer

voidamdgpu_vm_prt_cb(structdma_fence*fence,structdma_fence_cb*_cb)

callback for updating the PRT status

Parameters

structdma_fence*fence

fence for the callback

structdma_fence_cb*_cb

the callback function

voidamdgpu_vm_add_prt_cb(structamdgpu_device*adev,structdma_fence*fence)

add callback for updating the PRT status

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structdma_fence*fence

fence for the callback

voidamdgpu_vm_free_mapping(structamdgpu_device*adev,structamdgpu_vm*vm,structamdgpu_bo_va_mapping*mapping,structdma_fence*fence)

free a mapping

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structamdgpu_vm*vm

requested vm

structamdgpu_bo_va_mapping*mapping

mapping to be freed

structdma_fence*fence

fence of the unmap operation

Description

Free a mapping and make sure we decrease the PRT usage count if applicable.

voidamdgpu_vm_prt_fini(structamdgpu_device*adev,structamdgpu_vm*vm)

finish all prt mappings

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structamdgpu_vm*vm

requested vm

Description

Register a cleanup callback to disable PRT support after VM dies.

intamdgpu_vm_clear_freed(structamdgpu_device*adev,structamdgpu_vm*vm,structdma_fence**fence)

clear freed BOs in the PT

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structamdgpu_vm*vm

requested vm

structdma_fence**fence

optional resulting fence (unchanged if no work needed to be doneor if an error occurred)

Description

Make sure all freed BOs are cleared in the PT.PTs have to be reserved and mutex must be locked!

Return

0 for success.

intamdgpu_vm_handle_moved(structamdgpu_device*adev,structamdgpu_vm*vm,structww_acquire_ctx*ticket)

handle moved BOs in the PT

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structamdgpu_vm*vm

requested vm

structww_acquire_ctx*ticket

optional reservation ticket used to reserve the VM

Description

Make sure all BOs which are moved are updated in the PTs.

PTs have to be reserved!

Return

0 for success.

intamdgpu_vm_flush_compute_tlb(structamdgpu_device*adev,structamdgpu_vm*vm,uint32_tflush_type,uint32_txcc_mask)

Flush TLB on compute VM

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structamdgpu_vm*vm

requested vm

uint32_tflush_type

flush type

uint32_txcc_mask

mask of XCCs that belong to the compute partition in need of a TLB flush.

Description

Flush TLB if needed for a compute VM.

Return

0 for success.

structamdgpu_bo_va*amdgpu_vm_bo_add(structamdgpu_device*adev,structamdgpu_vm*vm,structamdgpu_bo*bo)

add a bo to a specific vm

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structamdgpu_vm*vm

requested vm

structamdgpu_bo*bo

amdgpu buffer object

Description

Addbo into the requested vm.Addbo to the list of bos associated with the vm

Object has to be reserved!

Return

Newly added bo_va or NULL for failure

voidamdgpu_vm_bo_insert_map(structamdgpu_device*adev,structamdgpu_bo_va*bo_va,structamdgpu_bo_va_mapping*mapping)

insert a new mapping

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structamdgpu_bo_va*bo_va

bo_va to store the address

structamdgpu_bo_va_mapping*mapping

the mapping to insert

Description

Insert a new mapping into all structures.

intamdgpu_vm_bo_map(structamdgpu_device*adev,structamdgpu_bo_va*bo_va,uint64_tsaddr,uint64_toffset,uint64_tsize,uint32_tflags)

map bo inside a vm

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structamdgpu_bo_va*bo_va

bo_va to store the address

uint64_tsaddr

where to map the BO

uint64_toffset

requested offset in the BO

uint64_tsize

BO size in bytes

uint32_tflags

attributes of pages (read/write/valid/etc.)

Description

Add a mapping of the BO at the specefied addr into the VM.

Object has to be reserved and unreserved outside!

Return

0 for success, error for failure.

intamdgpu_vm_bo_replace_map(structamdgpu_device*adev,structamdgpu_bo_va*bo_va,uint64_tsaddr,uint64_toffset,uint64_tsize,uint32_tflags)

map bo inside a vm, replacing existing mappings

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structamdgpu_bo_va*bo_va

bo_va to store the address

uint64_tsaddr

where to map the BO

uint64_toffset

requested offset in the BO

uint64_tsize

BO size in bytes

uint32_tflags

attributes of pages (read/write/valid/etc.)

Description

Add a mapping of the BO at the specefied addr into the VM. Replace existingmappings as we do so.

Object has to be reserved and unreserved outside!

Return

0 for success, error for failure.

intamdgpu_vm_bo_unmap(structamdgpu_device*adev,structamdgpu_bo_va*bo_va,uint64_tsaddr)

remove bo mapping from vm

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structamdgpu_bo_va*bo_va

bo_va to remove the address from

uint64_tsaddr

where to the BO is mapped

Description

Remove a mapping of the BO at the specefied addr from the VM.

Object has to be reserved and unreserved outside!

Return

0 for success, error for failure.

intamdgpu_vm_bo_clear_mappings(structamdgpu_device*adev,structamdgpu_vm*vm,uint64_tsaddr,uint64_tsize)

remove all mappings in a specific range

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structamdgpu_vm*vm

VM structure to use

uint64_tsaddr

start of the range

uint64_tsize

size of the range

Description

Remove all mappings in a range, split them as appropriate.

Return

0 for success, error for failure.

structamdgpu_bo_va_mapping*amdgpu_vm_bo_lookup_mapping(structamdgpu_vm*vm,uint64_taddr)

find mapping by address

Parameters

structamdgpu_vm*vm

the requested VM

uint64_taddr

the address

Description

Find a mapping by it’s address.

Return

The amdgpu_bo_va_mapping matching for addr or NULL

voidamdgpu_vm_bo_trace_cs(structamdgpu_vm*vm,structww_acquire_ctx*ticket)

trace all reserved mappings

Parameters

structamdgpu_vm*vm

the requested vm

structww_acquire_ctx*ticket

CS ticket

Description

Trace all mappings of BOs reserved during a command submission.

voidamdgpu_vm_bo_del(structamdgpu_device*adev,structamdgpu_bo_va*bo_va)

remove a bo from a specific vm

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structamdgpu_bo_va*bo_va

requested bo_va

Description

Removebo_va->bo from the requested vm.

Object have to be reserved!

boolamdgpu_vm_evictable(structamdgpu_bo*bo)

check if we can evict a VM

Parameters

structamdgpu_bo*bo

A page table of the VM.

Description

Check if it is possible to evict a VM.

voidamdgpu_vm_bo_invalidate(structamdgpu_bo*bo,boolevicted)

mark the bo as invalid

Parameters

structamdgpu_bo*bo

amdgpu buffer object

boolevicted

is the BO evicted

Description

Markbo as invalid.

voidamdgpu_vm_bo_move(structamdgpu_bo*bo,structttm_resource*new_mem,boolevicted)

handle BO move

Parameters

structamdgpu_bo*bo

amdgpu buffer object

structttm_resource*new_mem

the new placement of the BO move

boolevicted

is the BO evicted

Description

Update the memory stats for the new placement and markbo as invalid.

uint32_tamdgpu_vm_get_block_size(uint64_tvm_size)

calculate VM page table size as power of two

Parameters

uint64_tvm_size

VM size

Return

VM page table as power of two

voidamdgpu_vm_adjust_size(structamdgpu_device*adev,uint32_tmin_vm_size,uint32_tfragment_size_default,unsignedmax_level,unsignedmax_bits)

adjust vm size, block size and fragment size

Parameters

structamdgpu_device*adev

amdgpu_device pointer

uint32_tmin_vm_size

the minimum vm size in GB if it’s set auto

uint32_tfragment_size_default

Default PTE fragment size

unsignedmax_level

max VMPT level

unsignedmax_bits

max address space size in bits

longamdgpu_vm_wait_idle(structamdgpu_vm*vm,longtimeout)

wait for the VM to become idle

Parameters

structamdgpu_vm*vm

VM object to wait for

longtimeout

timeout to wait for VM to become idle

voidamdgpu_vm_put_task_info(structamdgpu_task_info*task_info)

reference down the vm task_info ptr

Parameters

structamdgpu_task_info*task_info

task_infostructunder discussion.

Description

frees the vm task_info ptr at the last put

structamdgpu_task_info*amdgpu_vm_get_task_info_vm(structamdgpu_vm*vm)

Extracts task info for a vm.

Parameters

structamdgpu_vm*vm

VM to get info from

Description

Returns the reference counted task_info structure, which must bereferenced down with amdgpu_vm_put_task_info.

structamdgpu_task_info*amdgpu_vm_get_task_info_pasid(structamdgpu_device*adev,u32pasid)

Extracts task info for a PASID.

Parameters

structamdgpu_device*adev

drm device pointer

u32pasid

PASID identifier for VM

Description

Returns the reference counted task_info structure, which must bereferenced down with amdgpu_vm_put_task_info.

voidamdgpu_vm_set_task_info(structamdgpu_vm*vm)

Sets VMs task info.

Parameters

structamdgpu_vm*vm

vm for which to set the info

intamdgpu_vm_init(structamdgpu_device*adev,structamdgpu_vm*vm,int32_txcp_id,uint32_tpasid)

initialize a vm instance

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structamdgpu_vm*vm

requested vm

int32_txcp_id

GPU partition selection id

uint32_tpasid

the pasid the VM is using on this GPU

Description

Initvm fields.

Return

0 for success, error for failure.

intamdgpu_vm_make_compute(structamdgpu_device*adev,structamdgpu_vm*vm)

Turn a GFX VM into a compute VM

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structamdgpu_vm*vm

requested vm

Description

This only works on GFX VMs that don’t have any BOs added and nopage tables allocated yet.

Changes the following VM parameters:- use_cpu_for_update- pte_supports_ats

Reinitializes the page directory to reflect the changed ATSsetting.

Return

0 for success, -errno for errors.

voidamdgpu_vm_fini(structamdgpu_device*adev,structamdgpu_vm*vm)

tear down a vm instance

Parameters

structamdgpu_device*adev

amdgpu_device pointer

structamdgpu_vm*vm

requested vm

Description

Tear downvm.Unbind the VM and remove all bos from the vm bo list

voidamdgpu_vm_manager_init(structamdgpu_device*adev)

init the VM manager

Parameters

structamdgpu_device*adev

amdgpu_device pointer

Description

Initialize the VM manager structures

voidamdgpu_vm_manager_fini(structamdgpu_device*adev)

cleanup VM manager

Parameters

structamdgpu_device*adev

amdgpu_device pointer

Description

Cleanup the VM manager and free resources.

intamdgpu_vm_ioctl(structdrm_device*dev,void*data,structdrm_file*filp)

Manages VMID reservation for vm hubs.

Parameters

structdrm_device*dev

drm device pointer

void*data

drm_amdgpu_vm

structdrm_file*filp

drm file pointer

Return

0 for success, -errno for errors.

boolamdgpu_vm_handle_fault(structamdgpu_device*adev,u32pasid,u32vmid,u32node_id,uint64_taddr,uint64_tts,boolwrite_fault)

graceful handling of VM faults.

Parameters

structamdgpu_device*adev

amdgpu device pointer

u32pasid

PASID of the VM

u32vmid

VMID, only used for GFX 9.4.3.

u32node_id

Node_id received in IH cookie. Only applicable forGFX 9.4.3.

uint64_taddr

Address of the fault

uint64_tts

Timestamp of the fault

boolwrite_fault

true is write fault, false is read fault

Description

Try to gracefully handle a VM fault. Return true if the fault was handled andshouldn’t be reported any more.

voidamdgpu_debugfs_vm_bo_info(structamdgpu_vm*vm,structseq_file*m)

print BO info for the VM

Parameters

structamdgpu_vm*vm

Requested VM for printing BO info

structseq_file*m

debugfs file

Description

Print BO information in debugfs file for the VM

voidamdgpu_vm_update_fault_cache(structamdgpu_device*adev,unsignedintpasid,uint64_taddr,uint32_tstatus,unsignedintvmhub)

update cached fault into.

Parameters

structamdgpu_device*adev

amdgpu device pointer

unsignedintpasid

PASID of the VM

uint64_taddr

Address of the fault

uint32_tstatus

GPUVM fault status register

unsignedintvmhub

which vmhub got the fault

Description

Cache the fault info for later use by userspace in debugging.

boolamdgpu_vm_is_bo_always_valid(structamdgpu_vm*vm,structamdgpu_bo*bo)

check if the BO is VM always valid

Parameters

structamdgpu_vm*vm

VM to test against.

structamdgpu_bo*bo

BO to be tested.

Description

Returns true if the BO shares the dma_resv object with the root PD and isalways guaranteed to be valid inside the VM.

Interrupt Handling

Interrupts generated within GPU hardware raise interrupt requests that arepassed to amdgpu IRQ handler which is responsible for detecting source andtype of the interrupt and dispatching matching handlers. If handling aninterrupt requires calling kernel functions that may sleep processing isdispatched to work handlers.

If MSI functionality is not disabled by module parameter then MSIsupport will be enabled.

For GPU interrupt sources that may be driven by another driver, IRQ domainsupport is used (with mapping between virtual and hardware IRQs).

voidamdgpu_irq_disable_all(structamdgpu_device*adev)

disableall interrupts

Parameters

structamdgpu_device*adev

amdgpu device pointer

Description

Disable all types of interrupts from all sources.

irqreturn_tamdgpu_irq_handler(intirq,void*arg)

IRQ handler

Parameters

intirq

IRQ number (unused)

void*arg

pointer to DRM device

Description

IRQ handler for amdgpu driver (all ASICs).

Return

result of handling the IRQ, as defined byirqreturn_t

voidamdgpu_irq_handle_ih1(structwork_struct*work)

kick of processing for IH1

Parameters

structwork_struct*work

work structure instructamdgpu_irq

Description

Kick of processing IH ring 1.

voidamdgpu_irq_handle_ih2(structwork_struct*work)

kick of processing for IH2

Parameters

structwork_struct*work

work structure instructamdgpu_irq

Description

Kick of processing IH ring 2.

voidamdgpu_irq_handle_ih_soft(structwork_struct*work)

kick of processing for ih_soft

Parameters

structwork_struct*work

work structure instructamdgpu_irq

Description

Kick of processing IH soft ring.

boolamdgpu_msi_ok(structamdgpu_device*adev)

check whether MSI functionality is enabled

Parameters

structamdgpu_device*adev

amdgpu device pointer (unused)

Description

Checks whether MSI functionality has been disabled via module parameter(all ASICs).

Return

true if MSIs are allowed to be enabled orfalse otherwise

intamdgpu_irq_init(structamdgpu_device*adev)

initialize interrupt handling

Parameters

structamdgpu_device*adev

amdgpu device pointer

Description

Sets up work functions for hotplug and reset interrupts, enables MSIfunctionality, initializes vblank, hotplug and reset interrupt handling.

Return

0 on success or error code on failure

voidamdgpu_irq_fini_sw(structamdgpu_device*adev)

shut down interrupt handling

Parameters

structamdgpu_device*adev

amdgpu device pointer

Description

Tears down work functions for hotplug and reset interrupts, disables MSIfunctionality, shuts down vblank, hotplug and reset interrupt handling,turns off interrupts from all sources (all ASICs).

intamdgpu_irq_add_id(structamdgpu_device*adev,unsignedintclient_id,unsignedintsrc_id,structamdgpu_irq_src*source)

register IRQ source

Parameters

structamdgpu_device*adev

amdgpu device pointer

unsignedintclient_id

client id

unsignedintsrc_id

source id

structamdgpu_irq_src*source

IRQ source pointer

Description

Registers IRQ source on a client.

Return

0 on success or error code otherwise

voidamdgpu_irq_dispatch(structamdgpu_device*adev,structamdgpu_ih_ring*ih)

dispatch IRQ to IP blocks

Parameters

structamdgpu_device*adev

amdgpu device pointer

structamdgpu_ih_ring*ih

interrupt ring instance

Description

Dispatches IRQ to IP blocks.

voidamdgpu_irq_delegate(structamdgpu_device*adev,structamdgpu_iv_entry*entry,unsignedintnum_dw)

delegate IV to soft IH ring

Parameters

structamdgpu_device*adev

amdgpu device pointer

structamdgpu_iv_entry*entry

IV entry

unsignedintnum_dw

size of IV

Description

Delegate the IV to the soft IH ring and schedule processing of it. Usedif the hardware delegation to IH1 or IH2 doesn’t work for some reason.

intamdgpu_irq_update(structamdgpu_device*adev,structamdgpu_irq_src*src,unsignedinttype)

update hardware interrupt state

Parameters

structamdgpu_device*adev

amdgpu device pointer

structamdgpu_irq_src*src

interrupt source pointer

unsignedinttype

type of interrupt

Description

Updates interrupt state for the specific source (all ASICs).

voidamdgpu_irq_gpu_reset_resume_helper(structamdgpu_device*adev)

update interrupt states on all sources

Parameters

structamdgpu_device*adev

amdgpu device pointer

Description

Updates state of all types of interrupts on all sources on resume afterreset.

intamdgpu_irq_get(structamdgpu_device*adev,structamdgpu_irq_src*src,unsignedinttype)

enable interrupt

Parameters

structamdgpu_device*adev

amdgpu device pointer

structamdgpu_irq_src*src

interrupt source pointer

unsignedinttype

type of interrupt

Description

Enables specified type of interrupt on the specified source (all ASICs).

Return

0 on success or error code otherwise

intamdgpu_irq_put(structamdgpu_device*adev,structamdgpu_irq_src*src,unsignedinttype)

disable interrupt

Parameters

structamdgpu_device*adev

amdgpu device pointer

structamdgpu_irq_src*src

interrupt source pointer

unsignedinttype

type of interrupt

Description

Enables specified type of interrupt on the specified source (all ASICs).

Return

0 on success or error code otherwise

boolamdgpu_irq_enabled(structamdgpu_device*adev,structamdgpu_irq_src*src,unsignedinttype)

check whether interrupt is enabled or not

Parameters

structamdgpu_device*adev

amdgpu device pointer

structamdgpu_irq_src*src

interrupt source pointer

unsignedinttype

type of interrupt

Description

Checks whether the given type of interrupt is enabled on the given source.

Return

true if interrupt is enabled,false if interrupt is disabled or oninvalid parameters

intamdgpu_irqdomain_map(structirq_domain*d,unsignedintirq,irq_hw_number_thwirq)

create mapping between virtual and hardware IRQ numbers

Parameters

structirq_domain*d

amdgpu IRQ domain pointer (unused)

unsignedintirq

virtual IRQ number

irq_hw_number_thwirq

hardware irq number

Description

Current implementation assigns simple interrupt handler to the given virtualIRQ.

Return

0 on success or error code otherwise

intamdgpu_irq_add_domain(structamdgpu_device*adev)

create a linear IRQ domain

Parameters

structamdgpu_device*adev

amdgpu device pointer

Description

Creates an IRQ domain for GPU interrupt sourcesthat may be driven by another driver (e.g., ACP).

Return

0 on success or error code otherwise

voidamdgpu_irq_remove_domain(structamdgpu_device*adev)

remove the IRQ domain

Parameters

structamdgpu_device*adev

amdgpu device pointer

Description

Removes the IRQ domain for GPU interrupt sourcesthat may be driven by another driver (e.g., ACP).

unsignedintamdgpu_irq_create_mapping(structamdgpu_device*adev,unsignedintsrc_id)

create mapping between domain Linux IRQs

Parameters

structamdgpu_device*adev

amdgpu device pointer

unsignedintsrc_id

IH source id

Description

Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQUse this for components that generate a GPU interrupt, but are drivenby a different driver (e.g., ACP).

Return

Linux IRQ

IP Blocks

GPUs are composed of IP (intellectual property) blocks. TheseIP blocks provide various functionalities: display, graphics,video decode, etc. The IP blocks that comprise a particular GPUare listed in the GPU’s respective SoC file. amdgpu_device.cacquires the list of IP blocks for the GPU in use on initialization.It can then operate on this list to perform standard driver operationssuch as: init, fini, suspend, resume, etc.

IP block implementations are named using the following convention:<functionality>_v<version> (E.g.: gfx_v6_0).

enumamd_ip_block_type

Used to classify IP blocks by functionality.

Constants

AMD_IP_BLOCK_TYPE_COMMON

GPU Family

AMD_IP_BLOCK_TYPE_GMC

Graphics Memory Controller

AMD_IP_BLOCK_TYPE_IH

Interrupt Handler

AMD_IP_BLOCK_TYPE_SMC

System Management Controller

AMD_IP_BLOCK_TYPE_PSP

Platform Security Processor

AMD_IP_BLOCK_TYPE_DCE

Display and Compositing Engine

AMD_IP_BLOCK_TYPE_GFX

Graphics and Compute Engine

AMD_IP_BLOCK_TYPE_SDMA

System DMA Engine

AMD_IP_BLOCK_TYPE_UVD

Unified Video Decoder

AMD_IP_BLOCK_TYPE_VCE

Video Compression Engine

AMD_IP_BLOCK_TYPE_ACP

Audio Co-Processor

AMD_IP_BLOCK_TYPE_VCN

Video Core/Codec Next

AMD_IP_BLOCK_TYPE_MES

Micro-Engine Scheduler

AMD_IP_BLOCK_TYPE_JPEG

JPEG Engine

AMD_IP_BLOCK_TYPE_VPE

Video Processing Engine

AMD_IP_BLOCK_TYPE_UMSCH_MM

User Mode Scheduler for Multimedia

AMD_IP_BLOCK_TYPE_ISP

Image Signal Processor

AMD_IP_BLOCK_TYPE_RAS

Reliability, Availability, Serviceability

AMD_IP_BLOCK_TYPE_NUM

Total number of IP block types

enumDC_FEATURE_MASK

Bits that control DC feature defaults

Constants

DC_FBC_MASK

(0x1) disabled by default

DC_MULTI_MON_PP_MCLK_SWITCH_MASK

(0x2) enabled by default

DC_DISABLE_FRACTIONAL_PWM_MASK

(0x4) disabled by default

DC_PSR_MASK

(0x8) disabled by default for DCN < 3.1

DC_EDP_NO_POWER_SEQUENCING

(0x10) disabled by default

DC_DISABLE_LTTPR_DP1_4A

(0x20) disabled by default

DC_DISABLE_LTTPR_DP2_0

(0x40) disabled by default

DC_PSR_ALLOW_SMU_OPT

(0x80) disabled by default

DC_PSR_ALLOW_MULTI_DISP_OPT

(0x100) disabled by default

DC_REPLAY_MASK

(0x200) disabled by default for DCN < 3.1.4

enumDC_DEBUG_MASK

Bits that are useful for debugging the Display Core IP

Constants

DC_DISABLE_PIPE_SPLIT

(0x1) If set, disable pipe-splitting

DC_DISABLE_STUTTER

(0x2) If set, disable memory stutter mode

DC_DISABLE_DSC

(0x4) If set, disable display stream compression

DC_DISABLE_CLOCK_GATING

(0x8) If set, disable clock gating optimizations

DC_DISABLE_PSR

(0x10) If set, disable Panel self refresh v1 and PSR-SU

DC_FORCE_SUBVP_MCLK_SWITCH

(0x20) If set, force mclk switch in subvp, evenif mclk switch in vblank is possible

DC_DISABLE_MPO

(0x40) If set, disable multi-plane offloading

DC_ENABLE_DPIA_TRACE

(0x80) If set, enable trace logging for DPIA

DC_ENABLE_DML2

(0x100) If set, force usage of DML2, even if the DCN versiondoes not default to it.

DC_DISABLE_PSR_SU

(0x200) If set, disable PSR SU

DC_DISABLE_REPLAY

(0x400) If set, disable Panel Replay

DC_DISABLE_IPS

(0x800) If set, disable all Idle Power States, all the time.If more than one IPS debug bit is set, the lowest bit takesprecedence. For example, if DC_FORCE_IPS_ENABLE andDC_DISABLE_IPS_DYNAMIC are set, then DC_DISABLE_IPS_DYNAMIC takesprecedence.

DC_DISABLE_IPS_DYNAMIC

(0x1000) If set, disable all IPS, all the time,except when driver goes into suspend.

DC_DISABLE_IPS2_DYNAMIC

(0x2000) If set, disable IPS2 (IPS1 allowed) ifthere is an enabled display. Otherwise, enable all IPS.

DC_FORCE_IPS_ENABLE

(0x4000) If set, force enable all IPS, all the time.

DC_DISABLE_ACPI_EDID

(0x8000) If set, don’t attempt to fetch EDID foreDP display from ACPI _DDC method.

DC_DISABLE_HDMI_CEC

(0x10000) If set, disable HDMI-CEC feature in amdgpu driver.

DC_DISABLE_SUBVP_FAMS

(0x20000) If set, disable DCN Sub-Viewport & Firmware AssistedMemory Clock Switching (FAMS) feature in amdgpu driver.

DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE

(0x40000) If set, disable support for custombrightness curves

DC_HDCP_LC_FORCE_FW_ENABLE

(0x80000) If set, use HDCP Locality Check FWpath regardless of reported HW capabilities.

DC_HDCP_LC_ENABLE_SW_FALLBACK

(0x100000) If set, upon HDCP Locality Check FWpath failure, retry using legacy SW path.

DC_SKIP_DETECTION_LT

(0x200000) If set, skip detection link training

structamd_ip_funcs

general hooks for managing amdgpu IP Blocks

Definition:

struct amd_ip_funcs {    char *name;    int (*early_init)(struct amdgpu_ip_block *ip_block);    int (*late_init)(struct amdgpu_ip_block *ip_block);    int (*sw_init)(struct amdgpu_ip_block *ip_block);    int (*sw_fini)(struct amdgpu_ip_block *ip_block);    int (*early_fini)(struct amdgpu_ip_block *ip_block);    int (*hw_init)(struct amdgpu_ip_block *ip_block);    int (*hw_fini)(struct amdgpu_ip_block *ip_block);    void (*late_fini)(struct amdgpu_ip_block *ip_block);    int (*prepare_suspend)(struct amdgpu_ip_block *ip_block);    int (*suspend)(struct amdgpu_ip_block *ip_block);    int (*resume)(struct amdgpu_ip_block *ip_block);    void (*complete)(struct amdgpu_ip_block *ip_block);    bool (*is_idle)(struct amdgpu_ip_block *ip_block);    int (*wait_for_idle)(struct amdgpu_ip_block *ip_block);    bool (*check_soft_reset)(struct amdgpu_ip_block *ip_block);    int (*pre_soft_reset)(struct amdgpu_ip_block *ip_block);    int (*soft_reset)(struct amdgpu_ip_block *ip_block);    int (*post_soft_reset)(struct amdgpu_ip_block *ip_block);    int (*set_clockgating_state)(struct amdgpu_ip_block *ip_block, enum amd_clockgating_state state);    int (*set_powergating_state)(struct amdgpu_ip_block *ip_block, enum amd_powergating_state state);    void (*get_clockgating_state)(struct amdgpu_ip_block *ip_block, u64 *flags);    void (*dump_ip_state)(struct amdgpu_ip_block *ip_block);    void (*print_ip_state)(struct amdgpu_ip_block *ip_block, struct drm_printer *p);};

Members

name

Name of IP block

early_init

sets up early driver state (pre sw_init),does not configure hw - Optional

late_init

sets up late driver/hw state (post hw_init) - Optional

sw_init

sets up driver state, does not configure hw

sw_fini

tears down driver state, does not configure hw

early_fini

tears down stuff before dev detached from driver

hw_init

sets up the hw state

hw_fini

tears down the hw state

late_fini

final cleanup

prepare_suspend

handle IP specific changes to prepare for suspend(such as allocating any required memory)

suspend

handles IP specific hw/sw changes for suspend

resume

handles IP specific hw/sw changes for resume

complete

handles IP specific changes after resume

is_idle

returns current IP block idle status

wait_for_idle

poll for idle

check_soft_reset

check soft reset the IP block

pre_soft_reset

pre soft reset the IP block

soft_reset

soft reset the IP block

post_soft_reset

post soft reset the IP block

set_clockgating_state

enable/disable cg for the IP block

set_powergating_state

enable/disable pg for the IP block

get_clockgating_state

get current clockgating status

dump_ip_state

dump the IP state of the ASIC during a gpu hang

print_ip_state

print the IP state in devcoredump for each IP of the ASIC

Description

These hooks provide an interface for controlling the operational stateof IP blocks. After acquiring a list of IP blocks for the GPU in use,the driver can make chip-wide state changes by walking this list andmaking calls to hooks from each IP block. This list is ordered to ensurethat the driver initializes the IP blocks in a safe sequence.