OpenRISC Linux

This is a port of Linux to the OpenRISC class of microprocessors; the initialtarget architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).

For information about OpenRISC processors and ongoing development:

Build instructions for OpenRISC toolchain and Linux

In order to build and run Linux for OpenRISC, you’ll need at least a basictoolchain and, perhaps, the architectural simulator. Steps to get these bitsin place are outlined here.

  1. Toolchain

Toolchain binaries can be obtained from openrisc.io or our github releases page.Instructions for building the different toolchains can be found on openrisc.ioor Stafford’s toolchain build and release scripts.

  1. Building

Build the Linux kernel as usual:

make ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfigmake ARCH=openrisc CROSS_COMPILE="or1k-linux-"

If you want to embed initramfs in the kernel, also passCONFIG_INITRAMFS_SOURCE. For example:

make ARCH=openrisc CROSS_COMPILE="or1k-linux-" CONFIG_INITRAMFS_SOURCE="path/to/rootfs path/to/devnodes"

For more information on this, please checkRamfs, rootfs and initramfs.

  1. Running on FPGA (optional)

The OpenRISC community typically uses FuseSoC to manage building and programmingan SoC into an FPGA. The below is an example of programming a De0 Nanodevelopment board with the OpenRISC SoC. During the build FPGA RTL is codedownloaded from the FuseSoC IP cores repository and built using the FPGA vendortools. Binaries are loaded onto the board with openocd.

git clone https://github.com/olofk/fusesoccd fusesocsudo pip install -e .fusesoc initfusesoc build de0_nanofusesoc pgm de0_nanoopenocd -f interface/altera-usb-blaster.cfg \        -f board/or1k_generic.cfgtelnet localhost 4444> init> halt; load_image vmlinux ; reset

  1. Running on a Simulator (optional)

QEMU is a processor emulator which we recommend for simulating the OpenRISCplatform. Please follow the OpenRISC instructions on the QEMU website to getLinux running on QEMU. You can build QEMU yourself, but your Linux distributionlikely provides binary packages to support OpenRISC.

Terminology

In the code, the following particles are used on symbols to limit the scopeto more or less specific processor implementations:

openrisc:

the OpenRISC class of processors

or1k:

the OpenRISC 1000 family of processors

or1200:

the OpenRISC 1200 processor

History

18-11-2003 Matjaz Breskvar (phoenix@bsemi.com)

initial port of linux to OpenRISC/or32 architecture.all the core stuff is implemented and seams usable.

08-12-2003 Matjaz Breskvar (phoenix@bsemi.com)

complete change of TLB miss handling.rewrite of exceptions handling.fully functional sash-3.6 in default initrd.a much improved version with changes all around.

10-04-2004 Matjaz Breskvar (phoenix@bsemi.com)

a lot of bugfixes all over.ethernet support, functional http and telnet servers.running many standard linux apps.

26-06-2004 Matjaz Breskvar (phoenix@bsemi.com)

port to 2.6.x

30-11-2004 Matjaz Breskvar (phoenix@bsemi.com)

lots of bugfixes and enhancements.added opencores framebuffer driver.

09-10-2010 Jonas Bonn (jonas@southpole.se)

major rewrite to bring up to par with upstream Linux 2.6.36