Atomic Operation Control (ATOMCTL) Register¶

We Have Atomic Operation Control (ATOMCTL) Register.This register determines the effect of using a S32C1I instructionwith various combinations of:

1. With and without an Coherent Cache Controller whichcan do Atomic Transactions to the memory internally.

2. With and without An Intelligent Memory Controller whichcan do Atomic Transactions itself.

The Core comes up with a default value of for the three types of cache ops:

0x28: (WB: Internal, WT: Internal, BY:Exception)

On the FPGA Cards we typically simulate an Intelligent Memory controllerwhich can implement RCW transactions. For FPGA cards with an ExternalMemory controller we let it to the atomic operations internally whiledoing a Cached (WB) transaction and use the Memory RCW for un-cachedoperations.

For systems without an coherent cache controller, non-MX, we alwaysuse the memory controllers RCW, though non-MX controllers likelysupport the Internal Operation.

CUSTOMER-WARNING:

Virtually all customers buy their memory controllers from vendors thatdon’t support atomic RCW memory transactions and will likely want toconfigure this register to not use RCW.

Developers might find using RCW in Bypass mode convenient when testingwith the cache being bypassed; for example studying cache alias problems.

See Section 4.3.12.4 of ISA; Bits:

  WB     WT      BY5   4 | 3   2 | 1   0