RISC-V Linux User ABI

ISA string ordering in /proc/cpuinfo

The canonical order of ISA extension names in the ISA string is defined inChapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged ISA(Document Version 20191213).

The specification uses vague wording, such as should, when it comes to ordering,so for our purposes the following rules apply:

  1. Single-letter extensions come first, in canonical order.The canonical order is “IMAFDQLCBKJTPVH”.

  2. All multi-letter extensions will be separated from other extensions by anunderscore.

  3. Additional standard extensions (starting with ‘Z’) will be sorted aftersingle-letter extensions and before any higher-privileged extensions.

  4. For additional standard extensions, the first letter following the ‘Z’conventionally indicates the most closely related alphabeticalextension category. If multiple ‘Z’ extensions are named, they will beordered first by category, in canonical order, as listed above, thenalphabetically within a category.

  5. Standard supervisor-level extensions (starting with ‘S’) will be listedafter standard unprivileged extensions. If multiple supervisor-levelextensions are listed, they will be ordered alphabetically.

  6. Standard machine-level extensions (starting with ‘Zxm’) will be listedafter any lower-privileged, standard extensions. If multiple machine-levelextensions are listed, they will be ordered alphabetically.

  7. Non-standard extensions (starting with ‘X’) will be listed after all standardextensions. If multiple non-standard extensions are listed, they will beordered alphabetically.

An example string following the order is:

rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux

“isa” and “hart isa” lines in /proc/cpuinfo

The “isa” line in /proc/cpuinfo describes the lowest common denominator ofRISC-V ISA extensions recognized by the kernel and implemented on all harts. The“hart isa” line, in contrast, describes the set of extensions recognized by thekernel on the particular hart being described, even if those extensions may notbe present on all harts in the system.

In both lines, the presence of an extension guarantees only that the hardwarehas the described capability. Additional kernel support or policy changes may berequired before an extension’s capability is fully usable by userspace programs.Similarly, for S-mode extensions, presence in one of these lines does notguarantee that the kernel is taking advantage of the extension, or that thefeature will be visible in guest VMs managed by this kernel.

Inversely, the absence of an extension in these lines does not necessarily meanthe hardware does not support that feature. The running kernel may not recognizethe extension, or may have deliberately removed it from the listing.

Misaligned accesses

Misaligned scalar accesses are supported in userspace, but they may performpoorly. Misaligned vector accesses are only supported if the Zicclsm extensionis supported.

Pointer masking

Support for pointer masking in userspace (the Supm extension) is provided viathePR_SET_TAGGED_ADDR_CTRL andPR_GET_TAGGED_ADDR_CTRLprctl()operations. Pointer masking is disabled by default. To enable it, userspacemust callPR_SET_TAGGED_ADDR_CTRL with thePR_PMLEN field set to thenumber of mask/tag bits needed by the application.PR_PMLEN is interpretedas a lower bound; if the kernel is unable to satisfy the request, thePR_SET_TAGGED_ADDR_CTRL operation will fail. The actual number of tag bitsis returned inPR_PMLEN by thePR_GET_TAGGED_ADDR_CTRL operation.

Additionally, when pointer masking is enabled (PR_PMLEN is greater than 0),a tagged address ABI is supported, with the same interface and behavior asdocumented for AArch64 (AArch64 TAGGED ADDRESS ABI).