Definition:

struct nand_parameters {    const char *model;    bool supports_set_get_features;    bool supports_read_cache;    unsigned long set_feature_list[BITS_TO_LONGS(ONFI_FEATURE_NUMBER)];    unsigned long get_feature_list[BITS_TO_LONGS(ONFI_FEATURE_NUMBER)];    struct onfi_params *onfi;};

Members

model

Model name

supports_set_get_features

The NAND chip supports setting/getting features

supports_read_cache

The NAND chip supports read cache operations

set_feature_list

Bitmap of features that can be set

get_feature_list

Bitmap of features that can be get

onfi

ONFI specific parameters

Definition:

struct nand_id {    u8 data[NAND_MAX_ID_LEN];    int len;};

Members

data

buffer containing the id bytes.

len

ID length.

Definition:

struct nand_ecc_step_info {    int stepsize;    const int *strengths;    int nstrengths;};

Members

stepsize

data bytes per ECC step

strengths

array of supported strengths

nstrengths

number of supported strengths

Definition:

struct nand_ecc_caps {    const struct nand_ecc_step_info *stepinfos;    int nstepinfos;    int (*calc_ecc_bytes)(int step_size, int strength);};

Members

stepinfos

array of ECC step information

nstepinfos

number of ECC step information

calc_ecc_bytes

driver’s hook to calculate ECC bytes per step

Definition:

struct nand_ecc_ctrl {    enum nand_ecc_engine_type engine_type;    enum nand_ecc_placement placement;    enum nand_ecc_algo algo;    int steps;    int size;    int bytes;    int total;    int strength;    int prepad;    int postpad;    unsigned int options;    u8 *calc_buf;    u8 *code_buf;    void (*hwctl)(struct nand_chip *chip, int mode);    int (*calculate)(struct nand_chip *chip, const uint8_t *dat, uint8_t *ecc_code);    int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc);    int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf, int oob_required, int page);    int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page);    int (*read_page)(struct nand_chip *chip, uint8_t *buf, int oob_required, int page);    int (*read_subpage)(struct nand_chip *chip, uint32_t offs, uint32_t len, uint8_t *buf, int page);    int (*write_subpage)(struct nand_chip *chip, uint32_t offset, uint32_t data_len, const uint8_t *data_buf, int oob_required, int page);    int (*write_page)(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page);    int (*write_oob_raw)(struct nand_chip *chip, int page);    int (*read_oob_raw)(struct nand_chip *chip, int page);    int (*read_oob)(struct nand_chip *chip, int page);    int (*write_oob)(struct nand_chip *chip, int page);};

Members

engine_type

ECC engine type

placement

OOB bytes placement

algo

ECC algorithm

steps

number of ECC steps per page

size

data bytes per ECC step

bytes

ECC bytes per step

total

total number of ECC bytes per page

strength

max number of correctible bits per ECC step

prepad

padding information for syndrome based ECC generators

postpad

padding information for syndrome based ECC generators

options

ECC specific options (see NAND_ECC_XXX flags defined above)

calc_buf

buffer for calculated ECC, size is oobsize.

code_buf

buffer for ECC read from flash, size is oobsize.

hwctl

function to control hardware ECC generator. Must onlybe provided if an hardware ECC is available

calculate

function for ECC calculation or readback from ECC hardware

correct

function for ECC correction, matching to ECC generator (sw/hw).Should return a positive number representing the number ofcorrected bitflips, -EBADMSG if the number of bitflips exceedECC strength, or any other error code if the error is notdirectly related to correction.If -EBADMSG is returned the input buffers should be leftuntouched.

read_page_raw

function to read a raw page without ECC. This functionshould hide the specific layout used by the ECCcontroller and always return contiguous in-band andout-of-band data even if they’re not storedcontiguously on the NAND chip (e.g.NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band andout-of-band data).

write_page_raw

function to write a raw page without ECC. This functionshould hide the specific layout used by the ECCcontroller and consider the passed data as contiguousin-band and out-of-band data. ECC controller isresponsible for doing the appropriate transformationsto adapt to its specific layout (e.g.NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band andout-of-band data).

read_page

function to read a page according to the ECC generatorrequirements; returns maximum number of bitflips corrected inany single ECC step, -EIO hw error

read_subpage

function to read parts of the page covered by ECC;returns same asread_page()

write_subpage

function to write parts of the page covered by ECC.

write_page

function to write a page according to the ECC generatorrequirements.

write_oob_raw

function to write chip OOB data without ECC

read_oob_raw

function to read chip OOB data without ECC

read_oob

function to read chip OOB data

write_oob

function to write chip OOB data

Definition:

struct nand_sdr_timings {    u64 tBERS_max;    u32 tCCS_min;    u64 tPROG_max;    u64 tR_max;    u32 tALH_min;    u32 tADL_min;    u32 tALS_min;    u32 tAR_min;    u32 tCEA_max;    u32 tCEH_min;    u32 tCH_min;    u32 tCHZ_max;    u32 tCLH_min;    u32 tCLR_min;    u32 tCLS_min;    u32 tCOH_min;    u32 tCS_min;    u32 tDH_min;    u32 tDS_min;    u32 tFEAT_max;    u32 tIR_min;    u32 tITC_max;    u32 tRC_min;    u32 tREA_max;    u32 tREH_min;    u32 tRHOH_min;    u32 tRHW_min;    u32 tRHZ_max;    u32 tRLOH_min;    u32 tRP_min;    u32 tRR_min;    u64 tRST_max;    u32 tWB_max;    u32 tWC_min;    u32 tWH_min;    u32 tWHR_min;    u32 tWP_min;    u32 tWW_min;};

Members

tBERS_max

Block erase time

tCCS_min

Change column setup time

tPROG_max

Page program time

tR_max

Page read time

tALH_min

ALE hold time

tADL_min

ALE to data loading time

tALS_min

ALE setup time

tAR_min

ALE to RE# delay

tCEA_max

CE# access time

tCEH_min

CE# high hold time

tCH_min

CE# hold time

tCHZ_max

CE# high to output hi-Z

tCLH_min

CLE hold time

tCLR_min

CLE to RE# delay

tCLS_min

CLE setup time

tCOH_min

CE# high to output hold

tCS_min

CE# setup time

tDH_min

Data hold time

tDS_min

Data setup time

tFEAT_max

Busy time for Set Features and Get Features

tIR_min

Output hi-Z to RE# low

tITC_max

Interface and Timing Mode Change time

tRC_min

RE# cycle time

tREA_max

RE# access time

tREH_min

RE# high hold time

tRHOH_min

RE# high to output hold

tRHW_min

RE# high to WE# low

tRHZ_max

RE# high to output hi-Z

tRLOH_min

RE# low to output hold

tRP_min

RE# pulse width

tRR_min

Ready to RE# low (data only)

tRST_max

Device reset time, measured from the falling edge of R/B# to therising edge of R/B#.

tWB_max

WE# high to SR[6] low

tWC_min

WE# cycle time

tWH_min

WE# high hold time

tWHR_min

WE# high to RE# low

tWP_min

WE# pulse width

tWW_min

WP# transition to WE# low

Definition:

struct nand_nvddr_timings {    u64 tBERS_max;    u32 tCCS_min;    u64 tPROG_max;    u64 tR_max;    u32 tAC_min;    u32 tAC_max;    u32 tADL_min;    u32 tCAD_min;    u32 tCAH_min;    u32 tCALH_min;    u32 tCALS_min;    u32 tCAS_min;    u32 tCEH_min;    u32 tCH_min;    u32 tCK_min;    u32 tCS_min;    u32 tDH_min;    u32 tDQSCK_min;    u32 tDQSCK_max;    u32 tDQSD_min;    u32 tDQSD_max;    u32 tDQSHZ_max;    u32 tDQSQ_max;    u32 tDS_min;    u32 tDSC_min;    u32 tFEAT_max;    u32 tITC_max;    u32 tQHS_max;    u32 tRHW_min;    u32 tRR_min;    u32 tRST_max;    u32 tWB_max;    u32 tWHR_min;    u32 tWRCK_min;    u32 tWW_min;};

Members

tBERS_max

Block erase time

tCCS_min

Change column setup time

tPROG_max

Page program time

tR_max

Page read time

tAC_min

Access window of DQ[7:0] from CLK

tAC_max

Access window of DQ[7:0] from CLK

tADL_min

ALE to data loading time

tCAD_min

Command, Address, Data delay

tCAH_min

Command/Address DQ hold time

tCALH_min

W/R_n, CLE and ALE hold time

tCALS_min

W/R_n, CLE and ALE setup time

tCAS_min

Command/address DQ setup time

tCEH_min

CE# high hold time

tCH_min

CE# hold time

tCK_min

Average clock cycle time

tCS_min

CE# setup time

tDH_min

Data hold time

tDQSCK_min

Start of the access window of DQS from CLK

tDQSCK_max

End of the access window of DQS from CLK

tDQSD_min

Min W/R_n low to DQS/DQ driven by device

tDQSD_max

Max W/R_n low to DQS/DQ driven by device

tDQSHZ_max

W/R_n high to DQS/DQ tri-state by device

tDQSQ_max

DQS-DQ skew, DQS to last DQ valid, per access

tDS_min

Data setup time

tDSC_min

DQS cycle time

tFEAT_max

Busy time for Set Features and Get Features

tITC_max

Interface and Timing Mode Change time

tQHS_max

Data hold skew factor

tRHW_min

Data output cycle to command, address, or data input cycle

tRR_min

Ready to RE# low (data only)

tRST_max

Device reset time, measured from the falling edge of R/B# to therising edge of R/B#.

tWB_max

WE# high to SR[6] low

tWHR_min

WE# high to RE# low

tWRCK_min

W/R_n low to data output cycle

tWW_min

WP# transition to WE# low

Constants

NAND_SDR_IFACE

Single Data Rate interface

NAND_NVDDR_IFACE

Double Data Rate interface

Definition:

struct nand_interface_config {    enum nand_interface_type type;    struct nand_timings {        unsigned int mode;        union {            struct nand_sdr_timings sdr;            struct nand_nvddr_timings nvddr;        };    } timings;};

Members

type

type of the timing

timings

The timing information

timings.mode

Timing mode as defined in the specification

{unnamed_union}

anonymous

timings.sdr

Use it whentype isNAND_SDR_IFACE.

timings.nvddr

Use it whentype isNAND_NVDDR_IFACE.

Parameters

conststructnand_interface_config*conf

The data interface

Parameters

conststructnand_interface_config*conf

The data interface

Parameters

conststructnand_interface_config*conf

The data interface

Parameters

conststructnand_interface_config*conf

The data interface

Definition:

struct nand_op_cmd_instr {    u8 opcode;};

Members

opcode

the command to issue in one cycle

Definition:

struct nand_op_addr_instr {    unsigned int naddrs;    const u8 *addrs;};

Members

naddrs

length of theaddrs array

addrs

array containing the address cycles to issue

Definition:

struct nand_op_data_instr {    unsigned int len;    union {        void *in;        const void *out;    } buf;    bool force_8bit;};

Members

len

number of data bytes to move

buf

buffer to fill

buf.in

buffer to fill when reading from the NAND chip

buf.out

buffer to read from when writing to the NAND chip

force_8bit

force 8-bit access

Definition:

struct nand_op_waitrdy_instr {    unsigned int timeout_ms;};

Members

timeout_ms

maximum delay while waiting for the ready/busy pin in ms

Constants

NAND_OP_CMD_INSTR

command instruction

NAND_OP_ADDR_INSTR

address instruction

NAND_OP_DATA_IN_INSTR

data in instruction

NAND_OP_DATA_OUT_INSTR

data out instruction

NAND_OP_WAITRDY_INSTR

wait ready instruction

Definition:

struct nand_op_instr {    enum nand_op_instr_type type;    union {        struct nand_op_cmd_instr cmd;        struct nand_op_addr_instr addr;        struct nand_op_data_instr data;        struct nand_op_waitrdy_instr waitrdy;    } ctx;    unsigned int delay_ns;};

Members

type

the instruction type

ctx

extra data associated to the instruction. You’ll have to use theappropriate element depending ontype

ctx.cmd

use it iftype isNAND_OP_CMD_INSTR

ctx.addr

use it iftype isNAND_OP_ADDR_INSTR

ctx.data

use it iftype isNAND_OP_DATA_IN_INSTRorNAND_OP_DATA_OUT_INSTR

ctx.waitrdy

use it iftype isNAND_OP_WAITRDY_INSTR

delay_ns

delay the controller should apply after the instruction has beenissued on the bus. Most modern controllers have internal timingscontrol logic, and in this case, the controller driver can ignorethis field.

Definition:

struct nand_subop {    unsigned int cs;    const struct nand_op_instr *instrs;    unsigned int ninstrs;    unsigned int first_instr_start_off;    unsigned int last_instr_end_off;};

Members

cs

the CS line to select for this NAND sub-operation

instrs

array of instructions

ninstrs

length of theinstrs array

first_instr_start_off

offset to start from for the first instructionof the sub-operation

last_instr_end_off

offset to end at (excluded) for the last instructionof the sub-operation

Definition:

struct nand_op_parser_addr_constraints {    unsigned int maxcycles;};

Members

maxcycles

maximum number of address cycles the controller can issue in asingle step

Definition:

struct nand_op_parser_data_constraints {    unsigned int maxlen;};

Members

maxlen

maximum data length that the controller can handle in a single step

Definition:

struct nand_op_parser_pattern_elem {    enum nand_op_instr_type type;    bool optional;    union {        struct nand_op_parser_addr_constraints addr;        struct nand_op_parser_data_constraints data;    } ctx;};

Members

type

the instructuction type

optional

whether this element of the pattern is optional or mandatory

ctx

address or data constraint

ctx.addr

address constraint (number of cycles)

ctx.data

data constraint (data length)

Definition:

struct nand_op_parser_pattern {    const struct nand_op_parser_pattern_elem *elems;    unsigned int nelems;    int (*exec)(struct nand_chip *chip, const struct nand_subop *subop);};

Members

elems

array of pattern elements

nelems

number of pattern elements inelems array

exec

the function that will issue a sub-operation

Definition:

struct nand_op_parser {    const struct nand_op_parser_pattern *patterns;    unsigned int npatterns;};

Members

patterns

array of supported patterns

npatterns

length of thepatterns array

Definition:

struct nand_operation {    unsigned int cs;    bool deassert_wp;    const struct nand_op_instr *instrs;    unsigned int ninstrs;};

Members

cs

the CS line to select for this NAND operation

deassert_wp

set to true when the operation requires the WP pin to bede-asserted (ERASE, PROG, ...)

instrs

array of instructions to execute

ninstrs

length of theinstrs array

Definition:

struct nand_controller_ops {    int (*attach_chip)(struct nand_chip *chip);    void (*detach_chip)(struct nand_chip *chip);    int (*exec_op)(struct nand_chip *chip, const struct nand_operation *op, bool check_only);    int (*setup_interface)(struct nand_chip *chip, int chipnr, const struct nand_interface_config *conf);};

Members

attach_chip

this method is called after the NAND detection phase afterflash ID and MTD fields such as erase size, page size and OOBsize have been set up. ECC requirements are available ifprovided by the NAND chip or device tree. Typically used tochoose the appropriate ECC configuration and allocateassociated resources.This hook is optional.

detach_chip

free all resources allocated/claimed innand_controller_ops->attach_chip().This hook is optional.

exec_op

controller specific method to execute NAND operations.This method replaces chip->legacy.cmdfunc(),chip->legacy.{read,write}_{buf,byte,word}(),chip->legacy.dev_ready() and chip->legacy.waitfunc().

setup_interface

setup the data interface and timing. If chipnr is set toNAND_DATA_IFACE_CHECK_ONLY this means the configurationshould not be applied but only checked.This hook is optional.

Definition:

struct nand_controller {    struct mutex lock;    const struct nand_controller_ops *ops;    struct {        unsigned int data_only_read: 1;        unsigned int cont_read: 1;    } supported_op;    bool controller_wp;};

Members

lock

lock used to serialize accesses to the NAND controller

ops

NAND controller operations.

supported_op

NAND controller known-to-be-supported operations,only writable by the core after initial checking.

supported_op.data_only_read

The controller supports reading more data fromthe bus without restarting an entire read operation norchanging the column.

supported_op.cont_read

The controller supports sequential cache reads.

controller_wp

the controller is in charge of handling the WP pin.

Definition:

struct nand_legacy {    void __iomem *IO_ADDR_R;    void __iomem *IO_ADDR_W;    void (*select_chip)(struct nand_chip *chip, int cs);    u8 (*read_byte)(struct nand_chip *chip);    void (*write_byte)(struct nand_chip *chip, u8 byte);    void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len);    void (*read_buf)(struct nand_chip *chip, u8 *buf, int len);    void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl);    void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column, int page_addr);    int (*dev_ready)(struct nand_chip *chip);    int (*waitfunc)(struct nand_chip *chip);    int (*block_bad)(struct nand_chip *chip, loff_t ofs);    int (*block_markbad)(struct nand_chip *chip, loff_t ofs);    int (*set_features)(struct nand_chip *chip, int feature_addr, u8 *subfeature_para);    int (*get_features)(struct nand_chip *chip, int feature_addr, u8 *subfeature_para);    int chip_delay;    struct nand_controller dummy_controller;};

Members

IO_ADDR_R

address to read the 8 I/O lines of the flash device

IO_ADDR_W

address to write the 8 I/O lines of the flash device

select_chip

select/deselect a specific target/die

read_byte

read one byte from the chip

write_byte

write a single byte to the chip on the low 8 I/O lines

write_buf

write data from the buffer to the chip

read_buf

read data from the chip into the buffer

cmd_ctrl

hardware specific function for controlling ALE/CLE/nCE. Also usedto write command and address

cmdfunc

hardware specific function for writing commands to the chip.

dev_ready

hardware specific function for accessing device ready/busy line.If set to NULL no access to ready/busy is available and theready/busy information is read from the chip status register.

waitfunc

hardware specific function for wait on ready.

block_bad

check if a block is bad, using OOB markers

block_markbad

mark a block bad

set_features

set the NAND chip features

get_features

get the NAND chip features

chip_delay

chip dependent delay for transferring data from array to readregs (tR).

dummy_controller

dummy controller implementation for drivers that canonly control a single chip

Definition:

struct nand_chip_ops {    int (*suspend)(struct nand_chip *chip);    void (*resume)(struct nand_chip *chip);    int (*lock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);    int (*unlock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);    int (*setup_read_retry)(struct nand_chip *chip, int retry_mode);    int (*choose_interface_config)(struct nand_chip *chip, struct nand_interface_config *iface);};

Members

suspend

Suspend operation

resume

Resume operation

lock_area

Lock operation

unlock_area

Unlock operation

setup_read_retry

Set the read-retry mode (mostly needed for MLC NANDs)

choose_interface_config

Choose the best interface configuration

Definition:

struct nand_manufacturer {    const struct nand_manufacturer_desc *desc;    void *priv;};

Members

desc

The manufacturer description

priv

Private information for the manufacturer driver

Definition:

struct nand_secure_region {    u64 offset;    u64 size;};

Members

offset

Offset of the start of the secure region

size

Size of the secure region

Definition:

struct nand_chip {    struct nand_device base;    struct nand_id id;    struct nand_parameters parameters;    struct nand_manufacturer manufacturer;    struct nand_chip_ops ops;    struct nand_legacy legacy;    unsigned int options;    const struct nand_interface_config *current_interface_config;    struct nand_interface_config *best_interface_config;    unsigned int bbt_erase_shift;    unsigned int bbt_options;    unsigned int badblockpos;    unsigned int badblockbits;    struct nand_bbt_descr *bbt_td;    struct nand_bbt_descr *bbt_md;    struct nand_bbt_descr *badblock_pattern;    u8 *bbt;    unsigned int page_shift;    unsigned int phys_erase_shift;    unsigned int chip_shift;    unsigned int pagemask;    unsigned int subpagesize;    u8 *data_buf;    u8 *oob_poi;    struct {        unsigned int bitflips;        int page;    } pagecache;    unsigned long buf_align;    struct mutex lock;    unsigned int suspended : 1;    wait_queue_head_t resume_wq;    int cur_cs;    int read_retries;    struct nand_secure_region *secure_regions;    u8 nr_secure_regions;    struct {        bool ongoing;        unsigned int first_page;        unsigned int pause_page;        unsigned int last_page;    } cont_read;    struct nand_controller *controller;    struct nand_ecc_ctrl ecc;    void *priv;};

Members

base

Inherit from the generic NAND device

id

Holds NAND ID

parameters

Holds generic parameters under an easily readable form

manufacturer

Manufacturer information

ops

NAND chip operations

legacy

All legacy fields/hooks. If you develop a new driver, don’t even tryto use any of these fields/hooks, and if you’re modifying anexisting driver that is using those fields/hooks, you shouldconsider reworking the driver and avoid using them.

options

Various chip options. They can partly be set to inform nand_scanabout special functionality. See the defines for furtherexplanation.

current_interface_config

The currently used NAND interface configuration

best_interface_config

The best NAND interface configuration which fits boththe NAND chip and NAND controller constraints. Ifunset, the default reset interface configuration mustbe used.

bbt_erase_shift

Number of address bits in a bbt entry

bbt_options

Bad block table specific options. All options used here mustcome from bbm.h. By default, these options will be copied tothe appropriate nand_bbt_descr’s.

badblockpos

Bad block marker position in the oob area

badblockbits

Minimum number of set bits in a good block’s bad block markerposition; i.e., BBM = 11110111b is good when badblockbits = 7

bbt_td

Bad block table descriptor for flash lookup

bbt_md

Bad block table mirror descriptor

badblock_pattern

Bad block scan pattern used for initial bad block scan

bbt

Bad block table pointer

page_shift

Number of address bits in a page (column address bits)

phys_erase_shift

Number of address bits in a physical eraseblock

chip_shift

Number of address bits in one chip

pagemask

Page number mask = number of (pages / chip) - 1

subpagesize

Holds the subpagesize

data_buf

Buffer for data, size is (page size + oobsize)

oob_poi

pointer on the OOB area covered by data_buf

pagecache

Structure containing page cache related fields

pagecache.bitflips

Number of bitflips of the cached page

pagecache.page

Page number currently in the cache. -1 means no page iscurrently cached

buf_align

Minimum buffer alignment required by a platform

lock

Lock protecting the suspended field. Also used to serialize accessesto the NAND device

suspended

Set to 1 when the device is suspended, 0 when it’s not

resume_wq

wait queue to sleep if rawnand is in suspended state.

cur_cs

Currently selected target. -1 means no target selected, otherwise weshould always have cur_cs >= 0 && cur_cs <nanddev_ntargets().NAND Controller drivers should not modify this value, but they’reallowed to read it.

read_retries

The number of read retry modes supported

secure_regions

Structure containing the secure regions info

nr_secure_regions

Number of secure regions

cont_read

Sequential page read internals

cont_read.ongoing

Whether a continuous read is ongoing or not

cont_read.first_page

Start of the continuous read operation

cont_read.pause_page

End of the current sequential cache read operation

cont_read.last_page

End of the continuous read operation

controller

The hardware controller structure which is shared among multipleindependent devices

ecc

The ECC controller structure

priv

Chip private data

Parameters

structnand_chip*chip

The NAND chip

Definition:

struct nand_flash_dev {    char *name;    union {        struct {            uint8_t mfr_id;            uint8_t dev_id;        };        uint8_t id[NAND_MAX_ID_LEN];    };    unsigned int pagesize;    unsigned int chipsize;    unsigned int erasesize;    unsigned int options;    uint16_t id_len;    uint16_t oobsize;    struct {        uint16_t strength_ds;        uint16_t step_ds;    } ecc;};

Members

name

a human-readable name of the NAND chip

{unnamed_union}

anonymous

{unnamed_struct}

anonymous

mfr_id

manufacturer ID part of the full chip ID array (refers the samememory address asid[0])

dev_id

device ID part of the full chip ID array (refers the same memoryaddress asid[1])

id

full device ID array

pagesize

size of the NAND page in bytes; if 0, then the real page size (aswell as the eraseblock size) is determined from the extended NANDchip ID array)

chipsize

total chip size in MiB

erasesize

eraseblock size in bytes (determined from the extended ID if 0)

options

stores various chip bit options

id_len

The valid length of theid.

oobsize

OOB size

ecc

ECC correctability and step information from the datasheet.

ecc.strength_ds

The ECC correctability from the datasheet, same as theecc_strength_ds in nand_chip{}.

ecc.step_ds

The ECC step required by theecc.strength_ds, same as theecc_step_ds in nand_chip{}, also from the datasheet.For example, the “4bit ECC for each 512Byte” can be set withNAND_ECC_INFO(4, 512).

Parameters

unsignedintcommand

opcode to check

Parameters

structnand_chip*chip

NAND chip object

Description

Returns the pre-allocated page buffer after invalidating the cache. Thisfunction should be used by drivers that do not want to allocate their ownbounce buffer and still need such a buffer for specific operations (mostcommonly when reading OOB data only).

Be careful to never call this function in the write/write_oob path, becausethe core may have placed the data to be written out in this buffer.

Return

pointer to the page cache buffer

Parameters

u8*dst

destination buffer

unsignedintdst_off

bit offset at which the writing starts

constu8*src

source buffer

unsignedintsrc_off

bit offset at which the reading starts

unsignedintnbits

number of bits to copy fromsrc todst

Description

Copy bits from one memory region to another (overlap authorized).

Parameters

structnand_chip*chip

NAND chip object

unsignedintcs

the CS line to select. Note that this CS id is always from the chipPoV, not the controller one

Description

Select a NAND target so that further operations executed onchip go to theselected NAND target.

Parameters

structnand_chip*chip

NAND chip object

Description

Deselect the currently selected NAND target. The result of operationsexecuted onchip after the target has been deselected is undefined.

Parameters

structnand_chip*chip

NAND chip structure

unsignedlongtimeout_ms

Timeout in ms

Description

Poll the STATUS register using ->exec_op() until the RDY bit becomes 1.If that does not happen whitin the specified timeout, -ETIMEDOUT isreturned.

This helper is intended to be used when the controller does not have accessto the NAND R/B pin.

Be aware that calling this helper from an ->exec_op() implementation means->exec_op() must be re-entrant.

Return 0 if the NAND chip is ready, a negative error otherwise.

Parameters

structnand_chip*chip

NAND chip structure

structgpio_desc*gpiod

GPIO descriptor of R/B pin

unsignedlongtimeout_ms

Timeout in ms

Description

Poll the R/B GPIO pin until it becomes ready. If that does not happenwhitin the specified timeout, -ETIMEDOUT is returned.

This helper is intended to be used when the controller has access to theNAND R/B pin over GPIO.

Return 0 if the R/B pin indicates chip is ready, a negative error otherwise.

Parameters

structnand_chip*chip

The NAND chip

unsignedintpage

page to read

unsignedintoffset_in_page

offset within the page

void*buf

buffer used to store the data

unsignedintlen

length of the buffer

Description

This function issues a READ PAGE operation.This function does not select/unselect the CS line.

Returns 0 on success, a negative error code otherwise.

Parameters

structnand_chip*chip

The NAND chip

unsignedintoffset_in_page

offset within the page

void*buf

buffer used to store the data

unsignedintlen

length of the buffer

boolforce_8bit

force 8-bit bus access

Description

This function issues a CHANGE READ COLUMN operation.This function does not select/unselect the CS line.

Returns 0 on success, a negative error code otherwise.

Parameters

structnand_chip*chip

The NAND chip

unsignedintpage

page to read

unsignedintoffset_in_oob

offset within the OOB area

void*buf

buffer used to store the data

unsignedintlen

length of the buffer

Description

This function issues a READ OOB operation.This function does not select/unselect the CS line.

Returns 0 on success, a negative error code otherwise.

Parameters

structnand_chip*chip

The NAND chip

unsignedintpage

page to write

unsignedintoffset_in_page

offset within the page

constvoid*buf

buffer containing the data to write to the page

unsignedintlen

length of the buffer

Description

This function issues the first half of a PROG PAGE operation.This function does not select/unselect the CS line.

Returns 0 on success, a negative error code otherwise.

Parameters

structnand_chip*chip

The NAND chip

Description

This function issues the second half of a PROG PAGE operation.This function does not select/unselect the CS line.

Returns 0 on success, a negative error code otherwise.

Parameters

structnand_chip*chip

The NAND chip

unsignedintpage

page to write

unsignedintoffset_in_page

offset within the page

constvoid*buf

buffer containing the data to write to the page

unsignedintlen

length of the buffer

Description

This function issues a full PROG PAGE operation.This function does not select/unselect the CS line.

Returns 0 on success, a negative error code otherwise.

Parameters

structnand_chip*chip

The NAND chip

unsignedintoffset_in_page

offset within the page

constvoid*buf

buffer containing the data to send to the NAND

unsignedintlen

length of the buffer

boolforce_8bit

force 8-bit bus access

Description

This function issues a CHANGE WRITE COLUMN operation.This function does not select/unselect the CS line.

Returns 0 on success, a negative error code otherwise.

Parameters

structnand_chip*chip

The NAND chip

u8addr

address cycle to pass after the READID command

void*buf

buffer used to store the ID

unsignedintlen

length of the buffer

Description

This function sends a READID command and reads back the ID returned by theNAND.This function does not select/unselect the CS line.

Returns 0 on success, a negative error code otherwise.

Parameters

structnand_chip*chip

The NAND chip

u8*status

out variable to store the NAND status

Description

This function sends a STATUS command and reads back the status returned bythe NAND.This function does not select/unselect the CS line.

Returns 0 on success, a negative error code otherwise.

Parameters

structnand_chip*chip

The NAND chip

Description

This function sends a READ0 command to cancel the effect of the STATUScommand to avoid reading only the status until a new read command is sent.

This function does not select/unselect the CS line.

Returns 0 on success, a negative error code otherwise.

Parameters

structnand_chip*chip

The NAND chip

unsignedinteraseblock

block to erase

Description

This function sends an ERASE command and waits for the NAND to be readybefore returning.This function does not select/unselect the CS line.

Returns 0 on success, a negative error code otherwise.

Parameters

structnand_chip*chip

The NAND chip

Description

This function sends a RESET command and waits for the NAND to be readybefore returning.This function does not select/unselect the CS line.

Returns 0 on success, a negative error code otherwise.

Parameters

structnand_chip*chip

The NAND chip

void*buf

buffer used to store the data

unsignedintlen

length of the buffer

boolforce_8bit

force 8-bit bus access

boolcheck_only

do not actually run the command, only checks if thecontroller driver supports it

Description

This function does a raw data read on the bus. Usually used after launchinganother NAND operation likenand_read_page_op().This function does not select/unselect the CS line.

Returns 0 on success, a negative error code otherwise.

Parameters

structnand_chip*chip

The NAND chip

constvoid*buf

buffer containing the data to send on the bus

unsignedintlen

length of the buffer

boolforce_8bit

force 8-bit bus access

Description

This function does a raw data write on the bus. Usually used after launchinganother NAND operation likenand_write_page_begin_op().This function does not select/unselect the CS line.

Returns 0 on success, a negative error code otherwise.

Parameters

structnand_chip*chip

the NAND chip

conststructnand_op_parser*parser

patterns description provided by the controller driver

conststructnand_operation*op

the NAND operation to address

boolcheck_only

when true, the function only checks ifop can be handled butdoes not execute the operation

Description

Helper function designed to ease integration of NAND controller drivers thatonly support a limited set of instruction sequences. The supported sequencesare described inparser, and the framework takes care of splittingop intomultiple sub-operations (if required) and pass them back to the ->exec()callback of the matching pattern ifcheck_only is set to false.

NAND controller drivers should call this function from their own ->exec_op()implementation.

Returns 0 on success, a negative error code otherwise. A failure can becaused by an unsupported operation (none of the supported patterns is ableto handle the requested operation), or an error returned by one of thematching pattern->exec() hook.

Parameters

conststructnand_subop*subop

The entire sub-operation

unsignedintinstr_idx

Index of the instruction inside the sub-operation

Description

During driver development, one could be tempted to directly use the->addr.addrs field of address instructions. This is wrong as addressinstructions might be split.

Given an address instruction, returns the offset of the first cycle to issue.

Parameters

conststructnand_subop*subop

The entire sub-operation

unsignedintinstr_idx

Index of the instruction inside the sub-operation

Description

During driver development, one could be tempted to directly use the->addr->naddrs field of a data instruction. This is wrong as instructionsmight be split.

Given an address instruction, returns the number of address cycle to issue.

Parameters

conststructnand_subop*subop

The entire sub-operation

unsignedintinstr_idx

Index of the instruction inside the sub-operation

Description

During driver development, one could be tempted to directly use the->data->buf.{in,out} field of data instructions. This is wrong as datainstructions might be split.

Given a data instruction, returns the offset to start from.

Parameters

conststructnand_subop*subop

The entire sub-operation

unsignedintinstr_idx

Index of the instruction inside the sub-operation

Description

During driver development, one could be tempted to directly use the->data->len field of a data instruction. This is wrong as data instructionsmight be split.

Returns the length of the chunk of data to send/receive.

Parameters

structnand_chip*chip

The NAND chip

intchipnr

Internal die id

Description

Save the timings data structure, then apply SDR timings mode 0 (seenand_reset_interface for details), do the reset operation, and applyback the previous timings.

Returns 0 on success, a negative error code otherwise.

Parameters

structnand_chip*chip

nand chip info structure

uint8_t*buf

buffer to store read data

intoob_required

caller requires OOB data read to chip->oob_poi

intpage

page number to read

Description

Not for syndrome calculating ECC controllers, which use a special oob layout.

Parameters

structnand_chip*chip

NAND chip info structure

u8*buf

buffer to store read data

intoob_required

caller requires OOB data read to chip->oob_poi

intpage

page number to read

Description

This is a raw page read, ie. without any error detection/correction.Monolithic means we are requesting all the relevant data (main pluseventually OOB) to be loaded in the NAND cache and sent over thebus (from the NAND chip to the NAND controller) in a singleoperation. This is an alternative tonand_read_page_raw(), whichfirst reads the main data, and if the OOB data is requested too,then reads more data on the bus.

Parameters

structnand_chip*chip

nand chip info structure

uint8_t*buf

buffer to store read data

intoob_required

caller requires OOB data read to chip->oob_poi

intpage

page number to read

Description

Hardware ECC for large page chips, which requires the ECC data to beextracted from the OOB before the actual data is read.

Parameters

structnand_chip*chip

nand chip info structure

intpage

page number to read

Parameters

structnand_chip*chip

nand chip info structure

intpage

page number to write

Parameters

structnand_chip*chip

nand chip info structure

constuint8_t*buf

data buffer

intoob_required

must write chip->oob_poi to OOB

intpage

page number to write

Description

Not for syndrome calculating ECC controllers, which use a special oob layout.

Parameters

structnand_chip*chip

NAND chip info structure

constu8*buf

data buffer to write

intoob_required

must write chip->oob_poi to OOB

intpage

page number to write

Description

This is a raw page write, ie. without any error detection/correction.Monolithic means we are requesting all the relevant data (main pluseventually OOB) to be sent over the bus and effectively programmedinto the NAND chip arrays in a single operation. This is analternative tonand_write_page_raw(), which first sends the maindata, then eventually send the OOB data by latching more datacycles on the NAND bus, and finally sends the program command tosynchronyze the NAND chip cache.

Parameters

structdevice*dev

Device that will be parsed. Also used for managed allocations.

structgpio_desc***cs_array

Array of GPIO desc pointers allocated on success

unsignedint*ncs_array

Number of entries incs_array updated on success.return 0 on success, an error otherwise.

Parameters

structnand_chip*chip

nand chip info structure

conststructnand_ecc_caps*caps

ECC engine caps info structure

intoobavail

OOB size that the ECC engine can use

Description

Choose the ECC configuration according to following logic.

1. If both ECC step size and ECC strength are already set (usually by DT)then check if it is supported by this controller.

2. If the user provided the nand-ecc-maximize property, then select maximumECC strength.

3. Otherwise, try to match the ECC step size and ECC strength closestto the chip’s requirement. If available OOB size can’t fit the chiprequirement then fallback to the maximum ECC step size and ECC strength.

On success, the chosen ECC settings are set.

Parameters

structnand_chip*chip

NAND chip object

unsignedintmaxchips

number of chips to scan for.

structnand_flash_dev*ids

optional flash IDs table

Description

This fills out all the uninitialized function pointers with the defaults.The flash ID is read and the mtd/chip structures are filled with theappropriate values.

Parameters

structnand_chip*chip

NAND chip object

Parameters

structnand_chip*chip

NAND chip object

Description

Release chip lock and wake up anyone waiting on the device.

Parameters

structnand_chip*chip

NAND chip object

intpage

First page to start checking for bad block marker usage

Description

Returns an integer that corresponds to the page offset within a block, fora page that is used to store bad block markers. If no more pages areavailable, -EINVAL is returned.

Parameters

structnand_chip*chip

NAND chip object

loff_tofs

offset from device start

Description

Check, if the block is bad.

Parameters

structnand_chip*chip

NAND chip object

loff_toffset

Offset of the region to check

u64size

Size of the region to check

Description

Checks if the region is secured by comparing the offset and size with thelist of secure regions obtained from DT. Returns true if the region issecured else false.

Parameters

structnand_chip*chip

NAND chip structure

Description

Lock the device and its controller for exclusive access

Parameters

structnand_chip*chip

NAND chip object

Description

Check, if the device is write protected. The function expects, that thedevice is already selected.

Parameters

structnand_chip*chip

NAND chip object

uint8_t*oob

oob data buffer

size_tlen

oob data write length

structmtd_oob_ops*ops

oob ops structure

Parameters

structnand_chip*chip

NAND chip object

loff_tto

offset to write to

structmtd_oob_ops*ops

oob operation description structure

Description

NAND write out-of-band.

Parameters

structnand_chip*chip

NAND chip object

loff_tofs

offset from device start

Description

This is the default implementation, which can be overridden by a hardwarespecific driver. It provides the details for writing a bad block marker to ablock.

Parameters

structnand_chip*chip

NAND chip object

loff_tofs

offset of the block to mark bad

Parameters

structnand_chip*chip

NAND chip object

loff_tofs

offset from device start

Description

This function performs the generic NAND bad block marking steps (i.e., badblock table(s) and/or marker(s)). We only allow the hardware driver tospecify how to write bad block markers to OOB (chip->legacy.block_markbad).

We try operations in the following order:

1. erase the affected block, to allow OOB marker to be written cleanly

2. write bad block marker to OOB area of affected block (unless flagNAND_BBT_NO_OOB_BBM is present)

3. update the BBT

Note that we retain the first error encountered in (2) or (3), finish theprocedures, and dump the error in the end.

Parameters

structmtd_info*mtd

MTD device structure

loff_tofs

offset from device start

Description

Check if the block is marked as reserved.

Parameters

structnand_chip*chip

NAND chip object

loff_tofs

offset from device start

intallowbbt

1, if its allowed to access the bbt area

Description

Check, if the block is bad. Either by reading the bad block table orcalling of the scan function.

Parameters

structnand_chip*chip

NAND chip structure

unsignedlongtimeo

timeout

Description

Wait for command done. This is a helper function for nand_wait used whenwe are in interrupt context. May happen when in panic and trying to writean oops through mtdoops.

Parameters

structnand_chip*chip

The NAND chip

intchipnr

Internal die id

Description

Reset the Data interface and timings to ONFI mode 0.

Returns 0 for success or negative error code otherwise.

Parameters

structnand_chip*chip

The NAND chip

intchipnr

Internal die id

Description

Configure what has been reported to be the best data interface and NANDtimings supported by the chip and the driver.

Returns 0 for success or negative error code otherwise.

Parameters

structnand_chip*chip

the NAND chip

structnand_interface_config*iface

the interface configuration (can eventually be updated)

structnand_sdr_timings*spec_timings

specific timings, when not fitting the ONFI specification

Description

If specific timings are provided, use them. Otherwise, retrieve supportedtiming modes from ONFI information.

Parameters

structnand_chip*chip

the NAND chip

structnand_interface_config*iface

the interface configuration (can eventually be updated)

structnand_nvddr_timings*spec_timings

specific timings, when not fitting the ONFI specification

Description

If specific timings are provided, use them. Otherwise, retrieve supportedtiming modes from ONFI information.

Parameters

structnand_chip*chip

the NAND chip

structnand_interface_config*iface

the interface configuration (can eventually be updated)

Description

If specific timings are provided, use them. Otherwise, retrieve supportedtiming modes from ONFI information.

Parameters

structnand_chip*chip

The NAND chip

Description

Find the best data interface and NAND timings supported by the chipand the driver. Eventually let the NAND manufacturer driver propose his ownset of timings.

After this function nand_chip->interface_config is initialized with the besttiming mode available.

Returns 0 for success or negative error code otherwise.

Parameters

structnand_chip*chip

The NAND chip

u8*addrs

Array of address cycles to fill

unsignedintoffset_in_page

The offset in the page

Description

Fills the first or the first two bytes of theaddrs field dependingon the NAND bus width and the page size.

Returns the number of cycles needed to encode the column, or a negativeerror code in case one of the arguments is invalid.

Parameters

structnand_chip*chip

The NAND chip

u8page

parameter page to read

void*buf

buffer used to store the data

unsignedintlen

length of the buffer

Description

This function issues a READ PARAMETER PAGE operation.This function does not select/unselect the CS line.

Returns 0 on success, a negative error code otherwise.

Parameters

structnand_chip*chip

The NAND chip

u8feature

feature id

constvoid*data

4 bytes of data

Description

This function sends a SET FEATURES command and waits for the NAND to beready before returning.This function does not select/unselect the CS line.

Returns 0 on success, a negative error code otherwise.

Parameters

structnand_chip*chip

The NAND chip

u8feature

feature id

void*data

4 bytes of data

Description

This function sends a GET FEATURES command and waits for the NAND to beready before returning.This function does not select/unselect the CS line.

Returns 0 on success, a negative error code otherwise.

Definition:

struct nand_op_parser_ctx {    const struct nand_op_instr *instrs;    unsigned int ninstrs;    struct nand_subop subop;};

Members

instrs

array of all the instructions that must be addressed

ninstrs

length of theinstrs array

subop

Sub-operation to be passed to the NAND controller

Parameters

conststructnand_op_parser_pattern_elem*pat

the parser pattern element that matchesinstr

conststructnand_op_instr*instr

pointer to the instruction to check

unsignedint*start_offset

this is an in/out parameter. Ifinstr has already beensplit, thenstart_offset is the offset from which to start(either an address cycle or an offset in the data buffer).Conversely, if the function returns true (ie. instr must besplit), this parameter is updated to point to the firstdata/address cycle that has not been taken care of.

Description

Some NAND controllers are limited and cannot send X address cycles with aunique operation, or cannot read/write more than Y bytes at the same time.In this case, split the instruction that does not fit in a singlecontroller-operation into two or more chunks.

Returns true if the instruction must be split, false otherwise.Thestart_offset parameter is also updated to the offset at which the nextbundle of instruction must start (if an address or a data instruction).

Parameters

conststructnand_op_parser_pattern*pat

the pattern to test

structnand_op_parser_ctx*ctx

the parser context structure to match with the patternpat

Description

Check ifpat matches the set or a sub-set of instructions remaining inctx.Returns true if this is the case, false ortherwise. When true is returned,ctx->subop is updated with the set of instructions to be passed to thecontroller driver.

Parameters

structnand_chip*chip

NAND chip info structure

intaddr

feature address

u8*subfeature_param

the subfeature parameters, a four bytes array

Description

Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if theoperation cannot be handled.

Parameters

structnand_chip*chip

NAND chip info structure

intaddr

feature address

u8*subfeature_param

the subfeature parameters, a four bytes array

Description

Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if theoperation cannot be handled.

Parameters

structnand_chip*chip

nand chip info structure

u8*buf

buffer to store read data

intoob_required

caller requires OOB data read to chip->oob_poi

intpage

page number to read

Description

Returns -ENOTSUPP unconditionally.

Parameters

structnand_chip*chip

nand chip info structure

uint8_t*buf

buffer to store read data

intoob_required

caller requires OOB data read to chip->oob_poi

intpage

page number to read

Description

We need a special oob layout and handling even when OOB isn’t used.

Parameters

structnand_chip*chip

nand chip info structure

uint8_t*buf

buffer to store read data

intoob_required

caller requires OOB data read to chip->oob_poi

intpage

page number to read

Parameters

structnand_chip*chip

nand chip info structure

uint32_tdata_offs

offset of requested data within the page

uint32_treadlen

data length

uint8_t*bufpoi

buffer to store read data

intpage

page number to read

Parameters

structnand_chip*chip

nand chip info structure

uint8_t*buf

buffer to store read data

intoob_required

caller requires OOB data read to chip->oob_poi

intpage

page number to read

Description

Not for syndrome calculating ECC controllers which need a special oob layout.

Parameters

structnand_chip*chip

nand chip info structure

uint8_t*buf

buffer to store read data

intoob_required

caller requires OOB data read to chip->oob_poi

intpage

page number to read

Description

The hw generator calculates the error syndrome automatically. Therefore weneed a special oob layout and handling.

Parameters

structnand_chip*chip

NAND chip object

uint8_t*oob

oob destination address

structmtd_oob_ops*ops

oob ops structure

size_tlen

size of oob to transfer

Parameters

structnand_chip*chip

NAND chip object

intretry_mode

the retry mode to use

Description

Some vendors supply a special command to shift the Vt threshold, to be usedwhen there are too many bitflips in a page (i.e., ECC error). After settinga new threshold, the host should retry reading the page.

Parameters

structnand_chip*chip

NAND chip object

loff_tfrom

offset to read from

structmtd_oob_ops*ops

oob ops structure

Description

Internal function. Called with chip held.