Computer Science > Hardware Architecture
arXiv:2411.16238 (cs)
[Submitted on 25 Nov 2024]
Title:UVLLM: An Automated Universal RTL Verification Framework using LLMs
Authors:Yuchen Hu,Junhao Ye,Ke Xu,Jialin Sun,Shiyue Zhang,Xinyao Jiao,Dingrong Pan,Jie Zhou,Ning Wang,Weiwei Shan,Xinwei Fang,Xi Wang,Nan Guan,Zhe Jiang
View a PDF of the paper titled UVLLM: An Automated Universal RTL Verification Framework using LLMs, by Yuchen Hu and 13 other authors
View PDFHTML (experimental)Abstract:Verifying hardware designs in embedded systems is crucial but often labor-intensive and time-consuming. While existing solutions have improved automation, they frequently rely on unrealistic assumptions. To address these challenges, we introduce a novel framework, UVLLM, which combines Large Language Models (LLMs) with the Universal Verification Methodology (UVM) to relax these assumptions. UVLLM significantly enhances the automation of testing and repairing error-prone Register Transfer Level (RTL) codes, a critical aspect of verification development. Unlike existing methods, UVLLM ensures that all errors are triggered during verification, achieving a syntax error fix rate of 86.99% and a functional error fix rate of 71.92% on our proposed benchmark. These results demonstrate a substantial improvement in verification efficiency. Additionally, our study highlights the current limitations of LLM applications, particularly their reliance on extensive training data. We emphasize the transformative potential of LLMs in hardware design verification and suggest promising directions for future research in AI-driven hardware design methodologies. The Repo. of dataset and code:this https URL.
| Subjects: | Hardware Architecture (cs.AR) |
| Cite as: | arXiv:2411.16238 [cs.AR] |
| (orarXiv:2411.16238v1 [cs.AR] for this version) | |
| https://doi.org/10.48550/arXiv.2411.16238 arXiv-issued DOI via DataCite |
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View a PDF of the paper titled UVLLM: An Automated Universal RTL Verification Framework using LLMs, by Yuchen Hu and 13 other authors
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