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arxiv logo>cs> arXiv:2411.12710
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Computer Science > Hardware Architecture

arXiv:2411.12710 (cs)
[Submitted on 19 Nov 2024]

Title:Travel Time Based Task Mapping for NoC-Based DNN Accelerator

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Abstract:Network-on-Chip (NoC) based architectures are recently proposed to accelerate deep neural networks in specialized hardware. Given that the hardware configuration is fixed post-manufacture, proper task mapping attracts researchers' interest. We propose a travel time-based task mapping method that allocates uneven counts of tasks across different Processing Elements (PEs). This approach utilizes the travel time recorded in the sampling window and implicitly makes use of static NoC architecture information and dynamic NoC congestion status. Furthermore, we examine the effectiveness of our method under various configurations, including different mapping iterations, flit sizes, and NoC architecture. Our method achieves up to 12.1% improvement compared with even mapping and static distance mapping for one layer. For a complete NN example, our method achieves 10.37% and 13.75% overall improvements to row-major mapping and distance-based mapping, respectively. While ideal travel time-based mapping (post-run) achieves 10.37% overall improvements to row-major mapping, we adopt a sampling window to efficiently map tasks during the running, achieving 8.17% (sampling window 10) improvement.
Comments:Accepted to SAMOS 2024 (SAMOS XXIV International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation June 29 - July 4, 2024)
Subjects:Hardware Architecture (cs.AR)
Cite as:arXiv:2411.12710 [cs.AR]
 (orarXiv:2411.12710v1 [cs.AR] for this version)
 https://doi.org/10.48550/arXiv.2411.12710
arXiv-issued DOI via DataCite

Submission history

From: Yizhi Chen [view email]
[v1] Tue, 19 Nov 2024 18:25:35 UTC (4,626 KB)
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