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Journal of Optical Communications and Networking
Vol. 10,
Issue 2,
pp. A270-A285
(2018)
•https://doi.org/10.1364/JOCN.10.00A270

Optically Disaggregated Data Centers With Minimal Remote Memory Latency: Technologies, Architectures, and Resource Allocation [Invited]

Georgios Zervas, Hui Yuan, Arsalan Saljoghei, Qianqiao Chen, and Vaibhawa Mishra

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Author Affiliations

Georgios Zervas,¹Hui Yuan,¹Arsalan Saljoghei,¹Qianqiao Chen,¹and Vaibhawa Mishra¹

¹The authors are with the Department of Electronic and Electrical Engineering, University College London, London, UK (e-mail: g.zervas@ucl.ac.uk).

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Georgios Zervas, Hui Yuan, Arsalan Saljoghei, Qianqiao Chen, and Vaibhawa Mishra, "Optically Disaggregated Data Centers With Minimal Remote Memory Latency: Technologies, Architectures, and Resource Allocation [Invited]," J. Opt. Commun. Netw.10, A270-A285 (2018)
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About this Article
History
- Original Manuscript: August 9, 2017
- Revised Manuscript: December 1, 2017
- Manuscript Accepted: December 2, 2017
- Published: February 1, 2018
Virtual Issues
Journal of Optical Communications and Networking OFC 2017 (2018)

Abstract

Disaggregated rack-scale data centers have been proposed as the only promising avenue to break the barrier of the fixed CPU-to-memory proportionality caused by main-tray direct-attached conventional/traditional server-centric systems. However, memory disaggregation has stringent network requirements in terms of latency, energy efficiency, bandwidth, and bandwidth density. This paper identifies all the requirements and key performance indicators of a network to disaggregate IT resources while summarizing the progress and importance of optical interconnects. Crucially, it proposes a rack-and-cluster scale architecture, which supports the disaggregation of CPU, memory, storage, and/or accelerator blocks. Optical circuit switching forms the core of this architecture, whereas the end-points (IT resources) are equipped with on-chip programmable hybrid electrical packet/circuit switches. This architecture offers dynamically reconfigurable physical topology to form virtual ones, each embedded with a set of functions. It analyzes the latency overhead of disaggregated DDR4 (parallel) and the proposed hybrid memory cube (serial) memory elements on the conventional and the proposed architecture. A set of resource allocation algorithms are introduced to (1) optimally select disaggregated IT resources with the lowest possible latency, (2) pool them together by means of a virtual network interconnect, and (3) compose virtual disaggregated servers. Simulation findings show up to a 34% resource utilization increase over traditional data centers while highlighting the importance of the placement and locality among compute, memory, and storage resources. In particular, the network-aware locality-based resource allocation algorithm achieves as low as 15 ns, 95 ns, and 315 ns memory transaction round-trip latency on 63%, 22%, and 15% of the allocated virtual machines (VMs) accordingly while utilizing 100% of the CPU resources. Furthermore, a formulation to parameterize and evaluate the additional financial costs endured by disaggregation is reported. It is shown that the more diverse the VM requests are, the higher the net financial gain is. Finally, an experiment was carried out using silicon photonic midboard optics and an optical circuit switch, which demonstrates forward error correction free $10^{- 12}$ bit error rate performance on up to five-tier scale-out networks.

Full Article | PDF Article

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Journal of Optical Communications and Networking

Andrew Lord, Editor-in-Chief

Table I

Recent Demonstrations of Large Channel Count Integrated Transceivers^a

Channel × Bitrate	Bandwidth Density ( $Gb / s / {mm}^{2}$ )	Energy Efficiency (pJ/bit)	Net Data Rate (Gb/s)	Multiplexing	Reach (km)/BER	Optical Link	References
$4 \times 66 - 77 Gb / s$	9.1–10.6	*	264–308	WDM	$1 / 1.5 \times 10^{- 2}$	1550 nm/SMF	[27]
$8 \times 25 Gb / s$	0.2	22.5	200	Spatial	${2 / 1 \times 10}^{- 12}$	1310 nm/SMF	[28]
$10 \times 25 Gb / s$	6.25	*	250	WDM	*	1550 nm/SMF	[29]
$10 \times 83 - 88 Gb / s$	*	*	830–880	WDM	$4 / 3.8 \times 10^{- 3}$	1550 nm/SMF	[30]
$12 \times 25 Gb / s$	*	2	300	Spatial	$BTB / 1 \times 10^{- 12}$	1550 nm/SMF	[31]
$12 \times 12.5 Gb / s$	*	*	150	Spatial	$BTB / 1 \times 10^{- 12}$	MMF	[32]
$12 \times 28.4 Gb / s$	0.6	17	340	Spatial	*	850 nm/MMF	[33]
$12 \times 28 Gb / s$	1	*	336	Spatial	${0.1 / 1 \times 10}^{- 15}$	850 nm/MMF	[34]
$12 \times 25 Gb / s$	*	*	300	Spatial	$0.07 / *$	MMF	[35]
$12 \times 25 Gb / s$	0.37	10	240	Spatial	${BTB / 1 \times 10}^{- 12}$	850 nm/MMF	[36]
$12 \times 10 Gb / s$	0.187	*	120	Spatial	${0.1 / 1 \times 10}^{- 12}$	850 nm/MMF	[37]
$24 \times 28 Gb / s$	1	13.4	672	Spatial	$* / 1 \times 10^{- 12}$	*	[38]
$24 \times 15 Gb / s$	1	*	360	Spatial	0.1/*	850 nm/MMF	[39]
$24 \times 20 Gb / s$	15.9	7.3	480	Spatial	$* / 1 \times 10^{- 12}$	850 nm/MMF	[40]
$168 \times 8 Gb / s$	64	10	1344	Spatial	$0.3 / 1 \times 10^{- 12}$	1000 nm/MMF	[26]

^a Bold text, (pre-)commercial; BTB, back to back; *, not available.

Table II

Simulation Assumptions and VM Resource Request Profiles

Configurations	12 dRacks	6 dBoxes/dRack	8 dBricks/dBox		16 Units/dBrick
4 Cores/CPU Unit		4 GB/RAM Unit	64 GB/Storage Unit		8 I/Os per dBrick at 25 Gb/s
Request Requirements	Type 0	Type 1	Type 2	Type 3	Type 4	Type 5
Request Requirements	Random	High RAM	High CPU	Half and half	More RAM	More CPU
CPU and RAM	1–32 core	1–8 core	24–32 core	Type 1 (50%)	1–16 core	17–32 core
CPU and RAM	1–32 GB	24–32 GB	1–8 GB	Type 2 (50%)	17–32 GB	1–16 GB
CPU-RAM bandwidth (fixed for all requests)		5 Gb/s/unit		RAM-STO bandwidth (fixed for all requests)	1 Gb/s/unit
CPU-RAM round-trip latency		180–480 ns		RAM-STO round-trip latency	480–780 ns

Tables (4)

Table I

Recent Demonstrations of Large Channel Count Integrated Transceivers^a

Channel × Bitrate	Bandwidth Density ( $Gb / s / {mm}^{2}$ )	Energy Efficiency (pJ/bit)	Net Data Rate (Gb/s)	Multiplexing	Reach (km)/BER	Optical Link	References
$4 \times 66 - 77 Gb / s$	9.1–10.6	*	264–308	WDM	$1 / 1.5 \times 10^{- 2}$	1550 nm/SMF	[27]
$8 \times 25 Gb / s$	0.2	22.5	200	Spatial	${2 / 1 \times 10}^{- 12}$	1310 nm/SMF	[28]
$10 \times 25 Gb / s$	6.25	*	250	WDM	*	1550 nm/SMF	[29]
$10 \times 83 - 88 Gb / s$	*	*	830–880	WDM	$4 / 3.8 \times 10^{- 3}$	1550 nm/SMF	[30]
$12 \times 25 Gb / s$	*	2	300	Spatial	$BTB / 1 \times 10^{- 12}$	1550 nm/SMF	[31]
$12 \times 12.5 Gb / s$	*	*	150	Spatial	$BTB / 1 \times 10^{- 12}$	MMF	[32]
$12 \times 28.4 Gb / s$	0.6	17	340	Spatial	*	850 nm/MMF	[33]
$12 \times 28 Gb / s$	1	*	336	Spatial	${0.1 / 1 \times 10}^{- 15}$	850 nm/MMF	[34]
$12 \times 25 Gb / s$	*	*	300	Spatial	$0.07 / *$	MMF	[35]
$12 \times 25 Gb / s$	0.37	10	240	Spatial	${BTB / 1 \times 10}^{- 12}$	850 nm/MMF	[36]
$12 \times 10 Gb / s$	0.187	*	120	Spatial	${0.1 / 1 \times 10}^{- 12}$	850 nm/MMF	[37]
$24 \times 28 Gb / s$	1	13.4	672	Spatial	$* / 1 \times 10^{- 12}$	*	[38]
$24 \times 15 Gb / s$	1	*	360	Spatial	0.1/*	850 nm/MMF	[39]
$24 \times 20 Gb / s$	15.9	7.3	480	Spatial	$* / 1 \times 10^{- 12}$	850 nm/MMF	[40]
$168 \times 8 Gb / s$	64	10	1344	Spatial	$0.3 / 1 \times 10^{- 12}$	1000 nm/MMF	[26]

^a Bold text, (pre-)commercial; BTB, back to back; *, not available.

Algorithm 1.

NULB resource allocation algorithm

Require:

G

: Data center graphs,

C

: Data center config,

R

: Request

1: procedurenuLocalityBased (

G, C, R

)

available. Cpu \leftarrow find slots \geq 1

inC.CpuLocations

available. Mem \leftarrow find slots \geq 1

inC.MemLocations

available. Sto \leftarrow find slots \geq 1

inC.StoLocations

cr. Cpu \leftarrow \frac{R.Cpu}{available. Cpu}

▹ Cpu contention ratio

cr. Mem \leftarrow \frac{R.Cpu}{available. Mem}

▹ Memory contention ratio

cr. Sto \leftarrow \frac{R.Cpu}{available. Sto}

▹ Storage contention ratio

cr. Max \leftarrow \max (cr. Cpu, cr. Mem, cr. Sto)

▹ Find maximum contention ratio

loopIncrement \leftarrow C.nSlots \times C.nBlades

▹ Size of a rack

10: for each

c

c r

do ▹ To try multiple contention ratios

11:

s \leftarrow cr. Max

12:

cr. Max \leftarrow

Update to new maximum contention ratio

13: switch

s

14: caseCpu

15: if

available. Cpu < R.Cpu

then ▹ Inadequate Cpu resources

16:

ITallocation \leftarrow Failure

17:

ITfailureCause \leftarrow Cpu

18: else

19: while

slot \leq C.CpuResources

20:

[ITallocation, ITres] \leftarrow BFS (G, slot, R)

21: if

ITallocation = Success

then

22:

[NETallocation, NETres] \leftarrow

netAllocation

(G, C, R, ITres)

23: if

NETallocation = Success

then

24: break

25: else

26: Remove failure nodes in

G.ITres

27: end if

28: else

29: Evaluate failure cause

30: UpdateITfailureCause

31: break

32: end if

33:

slot \leftarrow slot + loopIncrement

34: end while

35: end if

36: if

ITallocation = Success

and

NETallocation = Success

then

37: break

38: end if

39: caseMem

40: if

available. Mem < R.Mem

then

▹

Inadequate memory resources

41:

ITallocation \leftarrow Failure

42:

ITfailureCause \leftarrow Mem

43: else

44: while

slot \leq C MemResources

45:

[ITallocation, ITres] \leftarrow BFS (G, slot, R)

46: if

ITallocation = Success

then

47:

[NETallocation, NETres] \leftarrow

netAllocation (

G, C, R, I T r e s

)

48: if

NETallocation = Success

then

49: break

50: else

51: Remove failure nodes in

G . I T r e s

52: end if

53: else

54: Evaluate failure cause

55: UpdateITfailureCause

56: break

57: end if

58:

slot \leftarrow slot + loopIncrement

59: end while

60: end if

61: if

ITallocation = Success

and

NETallocation = Success

then

62: break

63: end if

64: caseSto

65: if

available. Sto < R.Sto

then

▹

Inadequate storage resources

66:

ITallocation \leftarrow Failure

67:

I T f a i l u r e C a u s e \leftarrow S t o

68: else

69: while

slot \leq C.StoResources

70:

[ITallocation, ITres] \leftarrow BFS (G, slot, R)

71: if

ITallocation = Success

then

72:

[NETallocation, NETres] \leftarrow

netAllocation(

G, C, R, ITres

)

73: if

NETallocation = Success

then

74: break

75: else

76: Remove failure nodes in

G.ITres

77: end if

78: else

79: Evaluate failure cause

80: UpdateITfailureCause

81: break

82: end if

83:

slot \leftarrow slot + loopIncrement

84: end while

85: end if

86: if

ITallocation = Success

and

NETallocation = Success

then

87: break

88: end if

89: if

ITallocation = Failure

then ▹ Inadequate IT resources

90: break

91: end if

92: end switch

93: end for

94: if

ITallocation = Success

and

NETallocation = Success

then

95: Update

C.ITres

▹ Remove allocated IT resources

96: UpdateG.bMap ▹ Remove allocated network resources

97: end ifreturnITallocation,ITres,NETallocation,NETres

98: end procedure

Algorithm 2.

Modified breadth-first search (mBFS) algorithm

Require:

G

: Data center graphs,

s

: Start vertex,

R

: Request

1: proceduremBFS (

G, s, R

)

bMap \leftarrow G.bMap

▹ Copy original bandwidth map

dMap \leftarrow G.dMap

▹ Copy original distance map

4: Remove all edges in

bMap

and

dMap

where

e_{b} < \min ({R.b}_{cm}, {R.b}_{ms})

5: for each vertex

v

G

do ▹ Initialize each vertex

v.distance \leftarrow \infty

v.parent \leftarrow null

8: end for

Q \leftarrow []

▹ Create an empty queue

10:

s.distance \leftarrow 0

11:

Q.enqueue (s)

▹ Enqueue start vertex

12:

ITres \leftarrow

Find IT resources on start vertex

s

13: while

Q \neq []

do ▹ Run until queue is empty

14:

current \leftarrow Q.dequeue ()

15:

neighbors \leftarrow

All vertices adjacent to

current

▹ High bandwidth links have a higher priority (network aware)

16:

{neighbors}^{'} \leftarrow

Sortneighbors in descending order

17: for each vertex

v

{neighbors}^{'}

18: if

v.distance = \infty

then

19:

v.distance \leftarrow current . distance + 1

20:

v.parent \leftarrow current

21:

Q.enqueue (v)

▹ Enqueue

v^{th}

neighbor

22:

ITres \leftarrow

Find IT resources on vertex

v

23: if

R . C p u

and

R . M e m

and

R . S t o

foundthen ▹ All resources found

24:

breakWhile \leftarrow True

25: break

26: end if

27: end if

28: end for

29: if

breakWhile \leftarrow True

then

30:

ITallocation \leftarrow Success

31:

ITfailureCause \leftarrow None

32: break

33: else

34:

I T a l l o c a t i o n \leftarrow F a i l u r e

35:

ITfailureCause \leftarrow

Evaluate failure cause

36: break

37: end if

38: end whilereturnITres,ITallocation

39: end procedure

Table II

Simulation Assumptions and VM Resource Request Profiles

Configurations	12 dRacks	6 dBoxes/dRack	8 dBricks/dBox		16 Units/dBrick
4 Cores/CPU Unit		4 GB/RAM Unit	64 GB/Storage Unit		8 I/Os per dBrick at 25 Gb/s
Request Requirements	Type 0	Type 1	Type 2	Type 3	Type 4	Type 5
Request Requirements	Random	High RAM	High CPU	Half and half	More RAM	More CPU
CPU and RAM	1–32 core	1–8 core	24–32 core	Type 1 (50%)	1–16 core	17–32 core
CPU and RAM	1–32 GB	24–32 GB	1–8 GB	Type 2 (50%)	17–32 GB	1–16 GB
CPU-RAM bandwidth (fixed for all requests)		5 Gb/s/unit		RAM-STO bandwidth (fixed for all requests)	1 Gb/s/unit
CPU-RAM round-trip latency		180–480 ns		RAM-STO round-trip latency	480–780 ns

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Movatterモバイル変換

Optically Disaggregated Data Centers With Minimal Remote Memory Latency: Technologies, Architectures, and Resource Allocation [Invited]

Author Affiliations

Abstract

Cited By

Figures (14)

Tables (4)

Equations (8)

Journal of Optical Communications and Networking

Table I

Recent Demonstrations of Large Channel Count Integrated Transceivers^a

Algorithm 1.

NULB resource allocation algorithm

Algorithm 2.

Modified breadth-first search (mBFS) algorithm

Table II

Simulation Assumptions and VM Resource Request Profiles

Tables (4)

Table I

Algorithm 1.

Algorithm 2.

Table II

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