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TLM modelling of 3D stacked wide I/O DRAM subsystems:a virtual platform for memory controller design space exploration
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Abstract
Three-dimensional stacked Wide I/O DRAMs have been proposed as a promising solution to overcome the pin-limited memory performance growth, the power vs. bandwidth dilemma and the Memory Wall. This new DRAM architecture and organisation requires a new generation of DRAM memory controllers.
In this paper, we present a new methodology using virtual platforms to model the backend of a 3D-DRAM memory subsystem (channel controller and Wide I/O DRAM) with specialSystemC TLM2.0 phase extensions. This methodology enables us to explore the complete design space of memory controllers at the system level at very fast simulation speeds with precise timing accuracy. We show simulation speedups of up to 377x with a timing accuracy of 99% compared to an equivalent cycle and pin accurateSystemC based RTL simulation.
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View all- Woo SElsasser WHamburg MLinstadt EMiller MSong TTringali J(2023)RAMPART: RowHammer Mitigation and Repair for Server Memory SystemsProceedings of the International Symposium on Memory Systems10.1145/3631882.3631886(1-15)Online publication date: 2-Oct-2023
- Srivastava GKaur PKaushik PGupta M(2023)Optimizing High Bandwidth Memory in Multi-Die Systems2023 IEEE Women in Technology Conference (WINTECHCON)10.1109/WINTECHCON58518.2023.10276441(1-5)Online publication date: 21-Sep-2023
- Steiner LJung MPrado FBykov KWehn N(2022)DRAMSys4.0: An Open-Source Simulation Framework for In-depth DRAM AnalysesInternational Journal of Parallel Programming10.1007/s10766-022-00727-450:2(217-242)Online publication date: 12-Mar-2022
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Index Terms
- TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration
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Published In
RAPIDO '13: Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
January 2013
49 pages
ISBN:9781450315395
DOI:10.1145/2432516
Copyright © 2013 ACM.
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Association for Computing Machinery
New York, NY, United States
Publication History
Published: 21 January 2013
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Cited By
View all- Woo SElsasser WHamburg MLinstadt EMiller MSong TTringali J(2023)RAMPART: RowHammer Mitigation and Repair for Server Memory SystemsProceedings of the International Symposium on Memory Systems10.1145/3631882.3631886(1-15)Online publication date: 2-Oct-2023
- Srivastava GKaur PKaushik PGupta M(2023)Optimizing High Bandwidth Memory in Multi-Die Systems2023 IEEE Women in Technology Conference (WINTECHCON)10.1109/WINTECHCON58518.2023.10276441(1-5)Online publication date: 21-Sep-2023
- Steiner LJung MPrado FBykov KWehn N(2022)DRAMSys4.0: An Open-Source Simulation Framework for In-depth DRAM AnalysesInternational Journal of Parallel Programming10.1007/s10766-022-00727-450:2(217-242)Online publication date: 12-Mar-2022
- Salem HTopham N(2021)Detecting denial-of-service hardware Trojans in DRAM-based memory systems2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)10.1109/ICECS53924.2021.9665634(1-6)Online publication date: 28-Nov-2021
- Mathew DKattan HWeis CHenkel JWehn NAmrouch H(2021)Longevity of Commodity DRAMs in Harsh Environments Through Thermoelectric CoolingIEEE Access10.1109/ACCESS.2021.30847499(83950-83962)Online publication date: 2021
- Steiner LJung MPrado FBykov KWehn N(2020)DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM SimulatorEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-030-60939-9_8(110-126)Online publication date: 7-Oct-2020
- Feldmann JKraft KSteiner LWehn NJung MDi Natale GFummi F(2020)Fast and accurate DRAM simulationProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408437(364-369)Online publication date: 9-Mar-2020
- Feldmann JKraft KSteiner LWehn NJung M(2020)Fast and Accurate DRAM Simulation: Can we Further Accelerate it?2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116275(364-369)Online publication date: Mar-2020
- Li SJacob B(2019)Statistical DRAM modelingProceedings of the International Symposium on Memory Systems10.1145/3357526.3357576(521-530)Online publication date: 30-Sep-2019
- Jung MKraft KSoliman TSudarshan CWeis CWehn N(2019)Fast validation of DRAM protocols with timed petri netsProceedings of the International Symposium on Memory Systems10.1145/3357526.3357556(133-147)Online publication date: 30-Sep-2019
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MatthiasJung
University of Kaiserslautern, Germany
ChristianWeis
University of Kaiserslautern, Germany
NorbertWehn
University of Kaiserslautern, Germany
KarthikChandrasekar
Delft University of Technology, Netherlands