This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bit-sliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500.

Authors and Affiliations

1. Key Laboratory of Computer System and Architecture, Chinese Academy of Sciences, Beijing, 100080, China

   Wei-Wu Hu, Ji-Ye Zhao, Shi-Qiang Zhong & Xu Yang

2. Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100080, China

   Wei-Wu Hu, Ji-Ye Zhao, Shi-Qiang Zhong & Xu Yang

3. ST Microelectronics, 39 Chemin du Camp-des-Filles, 1228 Plan Les Ouates, Geneva, Switzerland

   Elio Guidetti & Chris Wu

Corresponding author

Correspondence toWei-Wu Hu.

Supported by the National Natural Science Foundation of China for Distinguished Young Scholars under Grant No. 60325205, the National Natural Science Foundation of China under Grant No. 60673146, the National High Technology Development 863 Program of China under Grants No. 2002AA110010, No. 2005AA110010, No. 2005AA119020, and the National Grand Fundamental Research 973 Program of China under Grant No. 2005CB321600.

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