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Abstract
Maestro is a distributed shared memory system currently being developed. In this paper, an architecture of the high performance network interface of Maestro is presented. Maestro consists of multiple PC(Personal Computers and dedicated network hardware for high performance message passing and maintaining cache coherency. IEEE1394, a high performance serial link, is used in the physical layer of Maestro network. The network interface is developed using FPGA(Field Programmable Gate Array)s. A network latency and a bandwidth between the network interface and PC are measured and discussed.
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Authors and Affiliations
Institute of Information Sciences and Electronics, University of Tsukuba, Tsukuba, 305, Ibaraki, Japan
Shinichi Yamagiwa, Masaaki Ono, Takeshi Yamazaki, Pusit Kulkasem, Masayuki Hirota & Koichi Wada
- Shinichi Yamagiwa
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- Masaaki Ono
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- Takeshi Yamazaki
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- Pusit Kulkasem
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- Masayuki Hirota
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- Koichi Wada
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© 1998 Springer-Verlag Berlin Heidelberg
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Yamagiwa, S., Ono, M., Yamazaki, T., Kulkasem, P., Hirota, M., Wada, K. (1998). Maestro-link: A high performance interconnect for PC cluster. In: Hartenstein, R.W., Keevallik, A. (eds) Field-Programmable Logic and Applications From FPGAs to Computing Paradigm. FPL 1998. Lecture Notes in Computer Science, vol 1482. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0055273
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