Movatterモバイル変換


[0]ホーム

URL:


Skip to main content

Advertisement

Springer Nature Link
Log in

Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data

  • Conference paper

Abstract

In this work we consider coefficient reordering for low power realization of FIR filters on fixed-point multiply-accumulate (MAC) based architectures, such as DSP processors. Compared to previous work we consider the input data correlation in the ordering optimization. For this we model the input data using the dual bit type approach. Results show that compared with just optimizing the number of switches between coefficients, the proposed method works better when the input data is correlated, which can be assumed for most applications.

This is a preview of subscription content,log in via an institution to check access.

Access this chapter

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. Lapsley, P., Bier, J., Shoham, A., Lee, E.A.: DSP Processor Fundamentals: Architectures and Features. Wiley-IEEE Press (1997)

    Google Scholar 

  2. Wanhammar, L.: DSP Integrated Circuits. Academic Press, London (1999)

    Google Scholar 

  3. Meyer-Baese, U.: Digital Signal Processing with Field Programmable Gate Arrays. Springer, Heidelberg (2001)

    Google Scholar 

  4. Mehendale, M., Sherlekar, S.D., Venkatesh, G.: Low-power realization of FIR filters on programmable DSPs. IEEE Trans. VLSI Systems 6(4), 546–553 (1998)

    Article  Google Scholar 

  5. Gustafsson, O., Wanhammar, L.: Design of linear-phase FIR filters with minimum Hamming distance. In: Proc. IEEE Nordic Signal Processing Symp., October 4–7, 2002, Hurtigruten, Norway (2002)

    Google Scholar 

  6. Masselos, K., Merakos, P., Theoharis, S., Stouraitis, T., Goutis, C.E.: Power efficient data path synthesis of sum-of-products computations. IEEE Trans. VLSI Systems 11(3), 446–450 (2003)

    Article  Google Scholar 

  7. Arslan, T., Erdogan, A.T.: Data block processing for low power implementation of direct form FIR filters on single multiplier CMOS DSPs. In: Proc. IEEE Int. Symp. Circuits Syst., 1998, Monterey, CA, vol. 5, pp. 441–444 (1998)

    Google Scholar 

  8. Parhi, K.K.: Approaches to low-power implementations of DSP systems. IEEE Trans. Circuits Syst.–I 48(10), 1214–1224 (2001)

    Article  Google Scholar 

  9. Landman, P.E., Rabaey, J.M.: Architectural power analysis: The dual bit type method. IEEE Trans. VLSI Systems 3(2), 173–187 (1995)

    Article  Google Scholar 

  10. Ramprasad, S., Shanbhag, N.R., Hajj, I.N.: Analytical estimation of transition activity from word-level signal statistics. In: Proc. Design Automat. Conf., June 1997, 582–587 (1997)

    Google Scholar 

  11. Lundberg, M., Muhammad, K., Roy, K., Wilson, S.K.: A novel approach to high-level swithing activity modeling with applications to low-power DSP system synthesis. IEEE Trans. Signal Processing 49(12), 3157–3167 (2001)

    Article  Google Scholar 

  12. Gnu Linear Programming Kit 4.16,http://www.gnu.org/software/glpk/

  13. Hong, S., Chin, S.-S., Kim, S., Hwang, W.: Multiplier architecture power consumption characterization for low-power DSP applications. In: Proc. IEEE Int. Conf. Elec. Circuits Syst., September 15–18, 2002, Dubrovnik, Croatia (2002)

    Google Scholar 

  14. Oskuii, S.T., Kjeldsberg, P.G., Gustafsson, O.: Transition-activity aware design of reduction-stages for parallel multipliers. In: Proc. Great Lakes Symp. on VLSI, March 11–13, 2007, Stresa-Lago Maggiore, Italy (2007)

    Google Scholar 

  15. Caputa, P., Fredriksson, H., Hansson, M., Andersson, S., Alvandpour, A., Svensson, C.: An extended transition energy cost model for buses in deep submicron technologies. In: Proc. Int. Workshop on Power and Timing Modeling, Optimization and Simulation, Santorini, Greece, September 15–17, 2004, pp. 849–858 (2004)

    Google Scholar 

  16. Fischetti, M., Salazar Gonzâlez, J.J., Toth, P.: The generalized traveling salesman problem. In: The Traveling Salesman Problem and Its Variations, pp. 609–662. Kluwer Academic Publishers, Dordrecht (2002)

    Google Scholar 

  17. Kodek, D.M.: Performance limit of finite wordlength FIR digital filters. IEEE Trans. Signal Processing 53(7), 2462–2469 (2005)

    Article MathSciNet  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electrical Engineering, Linköping University, SE-581 83 Linköping, Sweden

    Oscar Gustafson & Kenny Johansson

  2. Department of Electronics and Telecommunications, Norwegian University of Science and Technology (NTNU), NO-7491 Trondheim, Norway

    Saeeid Tahmasbi Oskuii & Per Gunnar Kjeldsberg

Authors
  1. Oscar Gustafson

    You can also search for this author inPubMed Google Scholar

  2. Saeeid Tahmasbi Oskuii

    You can also search for this author inPubMed Google Scholar

  3. Kenny Johansson

    You can also search for this author inPubMed Google Scholar

  4. Per Gunnar Kjeldsberg

    You can also search for this author inPubMed Google Scholar

Editor information

Nadine Azémard Lars Svensson

Rights and permissions

Copyright information

© 2007 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Gustafson, O., Oskuii, S.T., Johansson, K., Kjeldsberg, P.G. (2007). Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data. In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_51

Download citation

Publish with us


[8]ページ先頭

©2009-2025 Movatter.jp