Movatterモバイル変換


[0]ホーム

URL:


Skip to main content

Advertisement

Springer Nature Link
Log in

A Bypass Mechanism to Enhance Branch Predictor for SMT Processors

  • Conference paper

Part of the book series:Lecture Notes in Computer Science ((LNTCS,volume 4697))

  • 952Accesses

Abstract

Unlike traditional superscalar processors, Simultaneous Multithreaded processors can explore both instruction level parallelism and thread level parallelism at the same time. With a same fetch width, SMT does not fetch instructions from a single thread as deeply as in traditional superscalar processors. Meanwhile, all the instructions from different threads share the same Function Units in SMT. All the characteristics make it possible to enhance the performance of SMT by reducing the branch mis-predictions. Based on the fact that about 15% of branch instructions directions can be definitely known at predicting cycle, a simple and effective bypass mechanism is proposed. This scheme doesn’t depend on any existing branch predictors, and it can be used as an effective enhancement to any one of them. Execution-driven simulation results show that the branch miss prediction rates of our predictor decrease by more than 15% on average compared to a simple base line (g-share) predictor and improve the instruction throughput by about 2.5%.

Supported by National Natural Science Foundation of China (NSFC) No.60573107.

This is a preview of subscription content,log in via an institution to check access.

Access this chapter

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. Tullsen, D.M., et al.: Simultaneous Multithreading:Maximizing On-Chip Parallelism. In: Proc. 22nd ISCA (June 1995)

    Google Scholar 

  2. Tullsen, D.M., et al.: Exploiting Choice:Instruction Fetch and Issure on an Implementable Simultaneous Multithreading Processor. In: Proc. 23rd ISCA (June 1996)

    Google Scholar 

  3. Swanson, S., et al.: An evaluation of speculative instruction execution on simultaneous multithreaded processors. ACM Transactions on Computer Systems archive 21(3) (2003)

    Google Scholar 

  4. Ramsay, M., et al.: Exploring Efficient SMT Branch Predictor DesignUniversity of Wisconsin-Madsin, Department of Electrical and Computer Engineering (2003)

    Google Scholar 

  5. Yeh, T.-Y., et al.: Two Level Adaptive Training Branch Prediction. In: 24th ACM/IEEE International Symposium on Micro architecture. pp. 51–61 (1991)

    Google Scholar 

  6. McFarling, S.: Combining Branch Predictors. Technical Report TN-36, Digital Western Research Laboratory (June 1993)

    Google Scholar 

  7. Lee, C.-C., Chen, I.-C.K., Mudge, T.N.: The Bi-Mode Branch Predictor. In: Proc. MICRO30 (December 1997)

    Google Scholar 

  8. Sprangle, E., et al.: The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference. In: Proc. 24th ISCA (May 1997)

    Google Scholar 

  9. Michaud, P., et al.: Trading Conflict and Capacity Aliasing in Conditional Branch Predictors. In: Proc. 24th ISCA (May 1997)

    Google Scholar 

  10. Chang, P.Y., et al.: Improving Branch Prediction Accuracy by Reducing Pattern History Table Interference. In: Proc. ICPACT (October 1996)

    Google Scholar 

  11. Eden, A.N., et al.: The YAGS Branch Prediction Scheme. In: Proc. 31st MICRO (December 1998)

    Google Scholar 

  12. Heil, T.H., et al.: Improving Branch Predictors by Correlating on Data Values. In: Proc. 25th ISCA (June 1998)

    Google Scholar 

  13. Tuck, N.,et al.: Multithreaded Value Prediction. In: Proc. of the 11th ISHPC (February 2005)

    Google Scholar 

  14. Calder, B., et al.: Selective Value Prediction. In: Proc. of the 26th ISCA (May 1999)

    Google Scholar 

  15. Lipasti, M.H., et al.: Value locality and data speculation. In: Proc. 7th International Conference on Architectural Support for Programming Languages and Operating Systems, October 1996, pp. 138–147 (1996)

    Google Scholar 

  16. Sazeides, Y., et al.: The predictability of data values. In: Proc. 30th MICRO (1997)

    Google Scholar 

  17. Vintan, L., et al.: An alternative to branch prediction: pre-computed branches. ACM SIGARCH Computer Architecture News archive 31, 20–29 (2003)

    Article  Google Scholar 

  18. Chappell, R., et al.: Difficult-path branch prediction using subordinate micro-threads. In: Proc. 29th ISCA (2003)

    Google Scholar 

  19. Zilles, C., et al.: Execution-based prediction using speculative slices. In: Proc. 28th ISCA (2001)

    Google Scholar 

  20. Vintan, L., et al.: Towards a High Performance Neural Branch Predictor. In: Proc. IJCNN 1999, Washington DC, USA (1999)

    Google Scholar 

  21. Thomas, R., et al.: Improving branch prediction by dynamic dataflow-based identification of correlated branches from a large global history. In: Proc. ICCA (2003)

    Google Scholar 

  22. Swanson, S., et al.: An evaluation of speculative instruction execution on simultaneous multithreaded processors. ACM Transactions on Computer Systems 21 (2003)

    Google Scholar 

  23. Tarjan, D., et al.: Merging path and g-share indexing in perceptron branch prediction. ACM Transactions on Computer Systems, 2 (September 2005)

    Google Scholar 

  24. Austin, T., et al.: SimpleScalar: An infrastructure for computer system modeling. IEEE Computer 35(2), 59–67 (2002)

    Google Scholar 

  25. He, L., et al.: A new value based branch predictor for SMT processors. In: Proc. 16th IASTED International Conference on Parallel and Distributed Computing and Systems (2004)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Computer Sciences, Northwestern Polytechnical University, China

    Yongfeng Pan, Xiaoya Fan & Deli Wang

  2. Department of Computer Sciences, University of Cyprus, Cyprus

    Liqiang He

Authors
  1. Yongfeng Pan

    You can also search for this author inPubMed Google Scholar

  2. Xiaoya Fan

    You can also search for this author inPubMed Google Scholar

  3. Liqiang He

    You can also search for this author inPubMed Google Scholar

  4. Deli Wang

    You can also search for this author inPubMed Google Scholar

Editor information

Lynn Choi Yunheung Paek Sangyeun Cho

Rights and permissions

Copyright information

© 2007 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Pan, Y., Fan, X., He, L., Wang, D. (2007). A Bypass Mechanism to Enhance Branch Predictor for SMT Processors. In: Choi, L., Paek, Y., Cho, S. (eds) Advances in Computer Systems Architecture. ACSAC 2007. Lecture Notes in Computer Science, vol 4697. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74309-5_34

Download citation

Publish with us


[8]ページ先頭

©2009-2025 Movatter.jp