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Abstract
Unlike traditional superscalar processors, Simultaneous Multithreaded processors can explore both instruction level parallelism and thread level parallelism at the same time. With a same fetch width, SMT does not fetch instructions from a single thread as deeply as in traditional superscalar processors. Meanwhile, all the instructions from different threads share the same Function Units in SMT. All the characteristics make it possible to enhance the performance of SMT by reducing the branch mis-predictions. Based on the fact that about 15% of branch instructions directions can be definitely known at predicting cycle, a simple and effective bypass mechanism is proposed. This scheme doesn’t depend on any existing branch predictors, and it can be used as an effective enhancement to any one of them. Execution-driven simulation results show that the branch miss prediction rates of our predictor decrease by more than 15% on average compared to a simple base line (g-share) predictor and improve the instruction throughput by about 2.5%.
Supported by National Natural Science Foundation of China (NSFC) No.60573107.
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Department of Computer Sciences, Northwestern Polytechnical University, China
Yongfeng Pan, Xiaoya Fan & Deli Wang
Department of Computer Sciences, University of Cyprus, Cyprus
Liqiang He
- Yongfeng Pan
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- Xiaoya Fan
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- Liqiang He
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- Deli Wang
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Pan, Y., Fan, X., He, L., Wang, D. (2007). A Bypass Mechanism to Enhance Branch Predictor for SMT Processors. In: Choi, L., Paek, Y., Cho, S. (eds) Advances in Computer Systems Architecture. ACSAC 2007. Lecture Notes in Computer Science, vol 4697. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74309-5_34
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