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Performance Analysis of BERT on RISC-V Processors with SIMD Units

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Abstract

Following the recent advances in open hardware generally, andRISC-V architectures particularly, we analyse the performance of transformer encoder inference on three low-power platforms with this type of architecture. For this purpose, we conduct a detailed profile of the inference process for two representative members of the BERT family, identifying the main bottlenecks and opportunities for optimisation on threeRISC-V processors equipped with floating-point SIMD (single instruction, multiple data) units: XuanTie C906, C908, and C910.

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Notes

  1. 1.

    The differences in the micro-kernel between both versions are minimal, replacing thevle/vse instructions by theirvle32/vse32 counterparts.

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Acknowledgements

Research funded by projects PID2020-113656RB-C22, PID2021-126576NB-I00, PID2021-123627OB-C52, TED2021-129334B-I00, TED2021-130123B-I00 (MCIN/AEI/10.13039/5011 00011033), GVA CIPROM/2022/20, UJI-2023-04. H. M. is a POSTDOC_21_00025 fellow supported by Junta de Andalucía. S. C. is supported by grant RYC2021-033973-I, funded by MCIN/AEI/10.13039/501100011033 and the EU "NextGenerationEU"/PRTR, and UJI-2023-04, funded by UJI.

Author information

Authors and Affiliations

  1. Universidad de Córdoba, Córdoba, Spain

    Héctor Martínez

  2. Universidad Complutense de Madrid, Madrid, Spain

    Carlos García & Francisco D. Igual

  3. Universidad de Castilla-La Mancha, Ciudad Real, Spain

    Rafael Rodríguez-Sánchez

  4. Universidad Jaume I de Castellón, Castelló de la Plana, Spain

    Sandra Catalán

  5. Universitat Politècnica de València, Valencia, Spain

    Adrián Castelló & Enrique S. Quintana-Ortí

Authors
  1. Héctor Martínez

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  2. Sandra Catalán

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  3. Carlos García

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  4. Francisco D. Igual

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  5. Rafael Rodríguez-Sánchez

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  6. Adrián Castelló

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  7. Enrique S. Quintana-Ortí

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Corresponding author

Correspondence toFrancisco D. Igual.

Editor information

Editors and Affiliations

  1. University of Edinburgh, Edinburgh, UK

    Michèle Weiland

  2. Johannes Gutenberg University Mainz, Mainz, Germany

    Sarah Neuwirth

  3. Cerfacs, Toulouse, France

    Carola Kruse

  4. Durham University, Durham, UK

    Tobias Weinzierl

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Martínez, H.et al. (2025). Performance Analysis of BERT on RISC-V Processors with SIMD Units. In: Weiland, M., Neuwirth, S., Kruse, C., Weinzierl, T. (eds) High Performance Computing. ISC High Performance 2024 International Workshops. ISC High Performance 2023. Lecture Notes in Computer Science, vol 15058. Springer, Cham. https://doi.org/10.1007/978-3-031-73716-9_23

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